Analog-to-Digital Converter - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 607

7 6 5 4 3 2 1 0

CCF6 CCF5 CCF4 CCF3

CCF7 CCF2 CCF1 CCF0

Reset: 0

CCFx: conversion complete flag x ( x = 7 , 0)
0 = conversion number x not completed.
1 = conversion number x has completed, result in ATD

0 0 0 0 0 0 0

y DR x ( y = 0 or 1).

Figure 12.15 ■ ATD status register 1 (ATD x STAT1, x 5 0 or 1)

A CCFx flag can be cleared by one of the following events:
• Writing to ATD x CTL5 (a new conversion is started)
• If AFFC 5 0 and read of ATD x STAT1 followed by read of result register ATD x DR y
• If AFFC 5 1 and read of result register ATD x DR y

ATD I NPUT E NABLE R EGISTER (ATD0DIEN, ATD1DIEN)
This register allows the user to enable a Port ADx pin as a digital input. The contents of
this register are shown in Figure 12.16.

7 6 5 4 3 2 1 0

IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0

Reset: 0 0 0 0 0 0 0 0

IEN x : ATD digital input enable on channel x ( x = 0 , 7)

0 = disable digital input buffer to PTAD x .
1 = enable digital input buffer to PTAD x .

Figure 12.16 ■ ATD input enable register (ATD x DIEN, x 5 0 or 1)

P ORT D ATA R EGISTER (PTAD0, PTAD1)
The data port associated with the ATD is input-only. The port pins are shared with the ana-
log inputs AN0,AN7 or AN8,AN15.

ATD C ONVERSION R ESULT R EGISTERS (ATD X DR Y , X 5 0 = 1, Y 5 0 = 7)
Each result register is 16-bit and can be further divided into two 8-bit registers, ATD x DRH y
and ATD x DRL y . Depending on the setting, the A/D conversion result can be stored right-justified
or left-justified. The conversion result can be signed or unsigned. However, the conversion result
is unsigned when it is stored right-justified.

12.4 The Functioning of the ATD Module

The operation of the ATD module is described in detail in this section.

12.4.1 Analog Input Multiplexer
The analog input multiplexer selects one of the external analog inputs to convert. The in-
put analog signals are unipolar and must fall within the potential range of V SSA and V DDA . The
input multiplexer includes protection circuitry to prevent crosstalk between channels when
the applied input potentials are within specification.