Hardware Reference
In-Depth Information
While in edge trigger mode, if additional active edges are detected while a conversion se-
quence is in progress the ETORF flag is set. This flag is cleared when one of the following
events occurs:
•
Writing a 1 to ETORF
•
Writing to ATD
x
CTL2, ATD
x
CTL3, or ATD
x
CTL4 (a conversion sequence is
aborted)
•
Writing to ATD
x
CTL5 (a new conversion sequence is started)
The setting of the FIFOR bit indicates that a result register has been written to before its
associated conversion complete flag (CCF) has been cleared. This flag is cleared when one of the
following events occurs:
•
Writing a 1 to FIFOR
•
Writing to ATD
x
CTL5
ATD T
EST
R
EGISTER
1 (ATD0TEST1, ATD1TEST1)
This register contains the SC bit used to enable special channel conversions. The contents
of this register are shown in Figure 12.14.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SC
0
0
0
0
0
0
0
0
Reset:
SC: special channel conversion bit
If this bit is set, the special channel conversion can be selected
using CC, CB, and CA of the ATD
x
CTL5 register. Table 12.7
shows the selection.
0 = special channel conversions disabled.
1 = special channel conversions enabled.
Figure 12.14
■
ATD test register 1 (ATD
x
TEST1,
x
5
0 or 1)
SC
CC
CB
CA
Analog Input Channel
1
1
1
1
1
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
Reserved
V
RH
V
RL
(V
RH
1
V
RL
)/2
Reserved
Table 12.7
■
Special channel select code
ATD S
TATUS
R
EGISTER
1 (ATD0STAT1, ATD1STAT1)
This read-only register contains the conversion complete flags for all channels. The con-
tents of this register are shown in Figure 12.15.
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