Hardware Reference
In-Depth Information
2
1
0
7
6
5
4
3
ADPU
AFFC
AWAI
ETRIGLE
ETRIGP
ETRIGE
ASCIE
ASCIF
Reset:
0
0
0
0
0
0
0
0
ADPU: ATD power-down bit
0 = power-down ATD.
1 = normal ATD operation.
AFFC: ATD fast flag clear all bit
0 = ATD flag is cleared normally, i.e., read the status register before reading the result
register.
1 = any access to a result register will cause the associated CCF flag to clear
automatically if it is set at the time.
AWAI: ATD power-down in wait-mode bit
0 = ATD continues to run when the HCS12 is in wait mode.
1 = halt conversion and power-down ATD during wait mode.
ETRIGLE: external trigger level/edge control
This bit controls the sensitivity of the external trigger signal. Details are shown in Table
12.1.
ETRIGP: external trigger polarity
This bit controls the polarity of the external trigger signal. See Table 12.1 for details.
ETRIGE: external trigger mode enable
0 = disable external trigger on ATD channel 7.
1 = enable external trigger on ATD channel 7.
ASCIE: ATD sequence complete interrupt enable bit
0 = disables ATD interrupt.
1 = enables ATD interrupt on sequence complete (ASCIF = 1).
ASCIF: ATD sequence complete interrupt flag
0 = no ATD interrupt occurred.
1 = ATD sequence complete, interrupt pending.
Figure 12.9
■
ATD control register 2 (ATD
x
CTL2,
x
5
0 or 1)
External Trigger
Sensitivity
ETRIGLE
ETRIGP
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Low level
High level
Table 12.1
■
External trigger configurations
There are two stages in the analog signal sample time. The first sample stage is fixed at
two conversion clock periods. The second stage is selected by SMP1 and SMP0 as shown in
Table 12.2.
ATD C
ONTROL
R
EGISTER
5 (ATD0CTL5, ATD1CTL5)
This register selects the type of conversion sequence and the analog input channels sam-
pled. Writes to this register will abort the current conversion sequence and start a new conver-
sion sequence. The contents of this register are shown in Figure 12.12.
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