Hardware Reference
In-Depth Information
12.3.1 Signal Pins Related to A/D Converter
Each of the two A/D modules has eight analog inputs. These input pins are labeled as
AN0,AN15. Pins AN0,AN7 are used by the converter AD0; AN8,AN15 are used by the con-
verter AD1. AN7 can optionally be used as the trigger input for AD0, and AN15 can optionally
be used as the trigger input for AD1. When a pin is not used as an input to the A/D converter, it
can be used as a general-purpose input pin.
The V RH and V RL pins are high-reference voltage and low-reference voltage inputs, respec-
tively. V DDA and V SSA are power supply inputs for the A/D converters.
12.3.2 Registers Associated with A/D Converter
Each A/D converter has the following registers:
Six control registers (ATD x CTL0,ATD x CTL5) that control the overall operation
of the module, two of which (ATD x CTL0 and ATD x CTL1) are intended for factory
testing only
Two status registers (ATD x STAT0 and ATD x STAT1) that record the operation
status of the converter
Two test registers (ATD x TEST0 and ATD x TEST1) that are dedicated to factory
testing purposes
One input enable register (ATD x DIEN) that enables analog pins to be used as
digital input
One port data register (PORTAD x or PTAD x )
Eight 16-bit result registers (ATD x DR0,ATD x DR7)
where x can be 0 or 1.
ATD C ONTROL R EGISTER 2 (ATD0CTL2, ATD1CTL2)
This register controls power-down, interrupt, and the external trigger. Writes to this reg-
ister will abort the current conversion sequence but will not start a new conversion sequence.
The contents of this register are shown in Figure 12.9.
ATD C ONTROL R EGISTER 3 (ATD0CTL3, ATD1CTL3)
This register sets the conversion sequence length, enables/disables the FIFO mode for
results registers, and controls the ATD behavior in freeze mode. Writes to this register will
abort the current conversion but will not start a new conversion. The contents of this register
are shown in Figure 12.10.
If the FIFO bit is 0, the A/D conversion results map into result registers on the basis of the
conversion sequence; the result of the first conversion appears in the first result register, the
second result in the second result register, and so on. If the FIFO bit is 1, the result of a conver-
sion will be stored in the result register specified by the conversion counter. The conversion
counter does not reset at the start of a new conversion sequence. The conversion counter value
is stored in the lowest 3 bits of the ATD status register 0.
ATD C ONTROL R EGISTER 4 (ATD0CTL4, ATD1CTL4)
This register sets the conversion clock frequency, the length of the second phase of the
sample time, and the resolution of the A/D conversion. Writes to this register will abort
the current conversion sequence but will not start a new sequence. The contents of this
register are shown in Figure 12.11.
 
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