Analog-to-Digital Converter - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 602

6

7 5 4 3 2 1 0

0
0

S8C S4C S2C S1C FIFO FRZ1 FRZ0

0 0

Reset: 0 0 0 0 0

S8C,S4C,S2C,S1C: conversion sequence limit
0000 = 8 conversions.
0001 = 1 conversion.
0010 = 2 conversions.
0011 = 3 conversions.
0100 = 4 conversions.
0101 = 5 conversions.
0110 = 6 conversions.
0111 = 7 conversions.
1xxx = 8 conversions.
FIFO: result register FIFO mode
0 = conversion results are placed in the corresponding result
register up to the selected sequence length.
1 = conversion results are placed in consecutive result registers
(wrap around at end).
FRZ1 and FRZ0: background debug (freeze) enable bit
00: continue conversions in active background mode.
01: reserved.
10: finish current conversion, then freeze.
11: freeze immediately when background mode is active.

Figure 12.10 ■ ATD control register 3 (ATD x CTL3, x 5 0 or 1)

6

7 5 4 3 2 1 0

SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0

Reset: 0 0 0 0 0 1 0 1

SRES8: ATD resolution select bit
0 = 10-bit operation.
1 = 8-bit operation.
SMP1 and SMP0: select sample time bits
These bits are used to select the length of the second phase of the
sample time in units of ATD conversion clock cycles. See Table
12.2.
PRS4-PRS0: ATD clock prescaler bits
These 5 bits are the binary value prescaler value PRS. The ATD
conversion clock frequency is calculated as follows:

E-clock
PRS + 1

ATDclock = × 0.5

The ATD conversion frequency must be between 500 kHz and 2
MHz. The clock prescaler values are shown in Table 12.3.

Figure 12.11 ■ ATD control register 4 (ATD x CTL4, x 5 0 or 1)