Inter-Integrated Circuit (I2C) Interface - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 544

7 6 5 4 3 2 1 0

TCF IBB 0 SRW

IAAS IBAL IBIF RXAK

Reset: 1 0 0 0 0 0 0 0

TCF: data transferring bit
0 = I 2 C transfer in progress.
1 = I 2 C transfer complete.
IAAS: addressed as a slave
0 = not addressed.
1 = addressed as a slave.
IBB: bus busy bit
0 = the bus enters idle state.
1 = I 2 C bus is busy.
IBAL: arbitration lost
0 = arbitration is not lost.
1 = arbitration is lost.
SRW: slave read/write
0 = slave receive, master writing to slave.
1 = slave transmit, master reading from slave.
IBIF: I 2 C bus interrupt
0 = no bus interrupt.
1 = bus interrupt.
RXAK: receive acknowledge
This bit reflects the value of SDA during the acknowledge bit of a cycle.
0 = acknowledge received.
1 = no acknowledge received.

Figure 11.24 ■ I 2 C status register (IBSR)

When a byte is being transferred, the TCF bit is cleared. It is set by the falling edge of the
ninth clock of a byte transfer.
The IAAS bit is set (when the I 2 C module is configured as a slave) when its own address is
matched with the calling address. The CPU may be interrupted if the IBIE bit is also set.
The IBB bit indicates the status of the I 2 C bus. When a start condition is detected, the IBB
bit will be set. When a stop condition is detected, this bit is cleared.
The IBAL bit indicates the recent loss in I 2 C bus arbitration. The arbitration is lost in the
following circumstances:
• The SDA signal is sampled low when the master drives a high during an address or
data transmit cycle.
• The SDA signal is sampled low when the master drives a high during the acknowledge
bit of a data receive cycle.
• A start cycle is attempted when the I 2 C bus is busy.
• A repeated start cycle is requested in slave mode.
• A stop condition is detected when the master did not request it.
When the IAAS bit is set, the SRW bit indicates the value of the R/W command bit of the
calling address sent from the master. The SRW bit is valid when the I 2 C module is in the slave
mode, a complete address transfer has occurred with an address match, and no other transfers
have been initiated.