Hardware Reference
In-Depth Information
7
6
5
4
3
2
1
0
IBEN
IBIE
MS/SL
Tx/Rx
TxAK
RSTA
0
IBSWAI
Reset:
0
0
0
0
0
0
0
0
IBEN: I
2
C bus enable
0 = I
2
C module is reset and disabled.
1 = I
2
C module is enabled. This bit must be set before any other IBCR bits have
any effect.
IBIE: I
2
C bus interrupt enable
0 = interrupts from the I
2
C module are disabled.
1 = interrupts from the I
2
C module enabled.
MS/SL: master/slave mode select
0 = slave mode.
1 = master mode.
Tx/Rx: transmit/receive mode select
0 = receive.
1 = transmit.
TxAK: transmit acknowledge
0 = an acknowledge signal will be sent out to the I
2
C bus on the 9th clock bit
after receiving 1 byte of data.
1 = no acknowledge signal response is sent.
RSTA: repeat start
0 = no action.
1 = generate a repeat start cycle.
IBSWAI: I
2
C bus stop in wait mode
0 = I
2
C module clock operates normally.
1 = stop generating I
2
C module clock in wait mode.
Figure 11.23
■
I
2
C control register (IBCR)
The Tx/Rx bit selects the direction of master and slave transfers. When addressed as a slave,
this bit should be set by software according to the SRW bit in the status register. In the master
mode, this bit should be set according to the type of transfer required. For address cycles, this
bit will always be high.
The TxAK bit specifies the value driven onto SDA during data acknowledge cycles for both
master and slave receivers. The I
2
C module will always acknowledge address matches, provided
it is enabled, regardless of the value of TxAK. Values written to this bit are only used when the
I
2
C module is a receiver, not a transmitter.
Writing a 1 to the RSTA bit will generate a repeated start condition on the I
2
C bus, pro-
vided it is the current master. This bit will always read as a low.
If the IBSWAI bit is set and the wai instruction is executed, all clock signals to the I
2
C
module will be stopped and any transmission currently in progress will halt. If the CPU were
woken up by a source other than the I
2
C module, then clocks would restart and the I
2
C would
continue where it left off in the previous transmission. If the IBSWAI bit were cleared when the
wai instruction is executed, the I
2
C internal clocks and interface would remain active, continu-
ing the operation that is currently underway. It is also possible to configure the I
2
C such that it
will wake up the CPU via an interrupt at the conclusion of the current operation.
This register records the status of all I
2
C data transmission/reception activities. The con-
tents of this register are shown in Figure 11.24.
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