Inter-Integrated Circuit (I2C) Interface - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 542

I 2 C
interrupt

Data bus

Address

ADDR_DECODE DATA_MUX

CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG

Input
sync

In/Out data
shift register

Start/Stop
arbitration
control

Clock
control

Address
compare

SCL SDL

Figure 11.21 ■ I 2 C block diagram

11.4 Registers for I 2 C Operation

11.4.1 The I 2 C Address Register (IBAD)
The IBAD register contains the address to which the I 2 C module will respond when it is
addressed as a slave. The contents of this register are shown in Figure 11.22.

7 6 5 4 3 2 1 0

ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0

Figure 11.22 ■ I 2 C address register (IBAD)

11.4.2 The I 2 C Control Register (IBCR)
This register controls all the operation parameters except the baud rate of the I 2 C module.
The contents of this register are shown in Figure 11.23.
When the MS/SL bit is changed from 0 to 1, a start signal is generated on the bus and the
master mode is selected. When this bit is changed from 1 to 0, a stop signal is generated and the
operation mode changes from master to slave. A stop signal should only be generated if the IBIF
flag is set.