Hardware Reference
In-Depth Information
The IBIF bit is set when one of the following conditions occurs:
Arbitration lost (IBAL bit is set).
Byte transfer complete (TCF bit is set).
Addressed as slave (IAAS bit is set).
This bit is cleared by writing a 1 to it.
11.4.4 I 2 C Data Register (IBDR)
In master transmit mode (the TxRx bit of the IBCR register set to 1), when data is written
into the IBDR register a data transfer is initiated. The most significant bit is sent out first. In
master receive mode, reading this register initiates the reception of the next byte. Nine clock
pulses will be sent out on the SCL pin to shift in 8 data bits and send out the acknowledge bit.
In slave mode, the same functions are available after an address match has occurred.
11.4.5 I 2 C Frequency Divider Register (IBFD)
The most important design consideration of the I 2 C module is to meet the timing require-
ments for the start and stop conditions so that data can be correctly transmitted over the bus
line. As illustrated in Figure 11.25, there are four timing requirements to be met.
SCL divider
SDA hold time
SCL hold time for start condition
SCL hold time for stop condition
SCL divider
SCL
SDA
SCL hold
(stop)
SCL hold (start)
SDA hold
SCL
SDA
Stop
condition
Start
condition
Figure 11.25 SCL divider and SDA hold
The requirements of these four parameters are listed in Table 11.2. The SCL divider is equal to
the bus frequency of the MCU divided by the SCL clock frequency.
Standard Mode
Fast Mode
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
f SCL
t HD;STA
t SU;STO
t HD;DAT
SCL clock frequency
SCL hold (start)
SCL hold (stop)
SDA hold
0
4.0
4.0
0
100
-
-
3.45
0
0.6
0.6
0
400
-
-
0.9
kHz
µs
µs
µs
Table 11.2 I 2 C bus timing requirements
 
 
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