Hardware Reference
In-Depth Information
However, none of them will be addressed because R/W 5 1 (for the 10-bit address)
or the 11110xx slave address (for the 7-bit address) does not match.
•
Combined format
. A master transmits data to a slave and then reads data from the
same slave (see Figure 11.18). The same master occupies the bus all the time. The
transfer direction is changed after the second R/W bit.
11110XX
0
Slave address
1st 7 bits
Slave address
2nd byte
S
R/W
A
A
Data
A
Data
A/A
(write)
11110XX
1
Slave address
1st 7 bits
R
R/W
A
Data
A
Data
A
P
(read)
Figure 11.18
■
Combined format: A master addresses a slave with a 10-bit address, then
transmits data to this slave and reads data from this slave
•
Combined format
. A master transmits data to one slave and then transmits data to
another slave (see Figure 11.19). The same master occupies the bus all the time.
11110XX
0
Slave address
1st 7 bits
Slave address
2nd byte
S
R/W
A
A
Data
A
Data
A/A
(write)
11110XX
0
Slave address
1st 7 bits
Slave address
2nd byte
R
R/W
Data
A
A/A
P
A
A
Data
(write)
Figure 11.19
■
Combined format: A master transmits data to two slaves, both with 10-bit addresses
•
Combined format
. Ten-bit and 7-bit addressing combined in one serial transfer
(see Figure 11.20). After each start (S) condition or each repeated start (R)
condition, a 10-bit or 7-bit slave address can be transmitted. Figure 11.20 shows
how a master transmits data to a slave with a 7-bit address and then transmits
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