Hardware Reference
In-Depth Information
A DDRESS M ARK W AKE -U P
In this wake-up method, a logic 1 in the most significant bit (msb) position of a frame clears
the RWU bit and wakes up the SCI. The logic 1 in the msb position marks a frame as an address
frame that contains addressing information. All receivers evaluate the addressing information,
and the receivers for which the message is addressed process the frames that follow. Any receiver
for which a message is not addressed can set its RWU bit and return to the standby state.
The logic 1 of an address frame clears the receiver's RWU bit before the stop bit is received
and sets the RDRF flag. Address mark wake-up allows messages to contain idle characters but
requires that the msb be reserved for use in address frames.
9.6.6 Single-Wire Operation
Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation,
the RxD pin is disconnected from the SCI module. The SCI module uses the TxD pin for both
receiving and transmitting, as illustrated in Figure 9.15.
Single-wire operation is enabled by setting the LOOPS and the RSRC bits in the SCI x CR1
register. Setting the LOOPS bit disables the path from the RxD pin to the receiver. Setting the
RSRC bit connects the receiver input to the output of the TxD pin driver. Both the transmitter
and receiver must be enabled. The TXDIR bit determines whether the TxD pin is going to be
used as an input (TXDIR 5 0) or an output (TXDIR 5 1) in this mode of operation.
Transmitter
TxD
Receiver
RxD
Figure 9.15 Single-wire operation
9.6.7 Loop Operation
In this operation, the transmitter output goes to the receiver input. As shown in Figure
9.16, the RxD signal is disconnected from the SCI. The loop operation is enabled by setting the
LOOPS bit and clearing the RSRC bit in the SCI x CR1 register. Setting the LOOPS bit disables
the path from the RxD pin to the receiver. Clearing the RSRC bit connects the transmitter out-
put to the receiver input. Both the transmitter and receiver must be enabled.
Transmitter
TxD
Receiver
RxD
Figure 9.16 Loop operation
 
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