Hardware Reference
In-Depth Information
Whenever one party in the data communication discovers an error, it can send break char-
acters to discontinue the communication and start over again. To send a break character, the
user sets the SBK bit in the SCI
x
CR1 register to 1. As long as the SBK bit is 1, transmitter logic
continuously loads break characters into the transmit shift register. After software clears the
SBK bit, the shift register finishes transmitting the last break character and then transmits at
least one logic 1. The automatic logic 1 at the end of a break character guarantees the recogni-
tion of the start bit of the next frame.
The SCI module recognizes a break character when a start bit is followed by 8 or 9 logic 0
data bits and a logic 0 where the stop bit should be. Receiving a break character has these ef-
fects on SCI registers.
•
Sets the framing error flag FE
•
Sets the receive data register full flag RDRF
•
Clears the SCI data registers (SCI
x
DRH/L)
•
May set the overrun flag OR, noise flag NF, parity error flag PE, or receiver active
flag RAF
An idle character contains all 1s and has no start, stop, or parity bit. The length of the idle
character depends on the M bit in the SCI
x
CR1 register. The preamble is a synchronizing idle
character that begins the first transmission initiated after setting the TE bit from 0 to 1.
If the TE bit is cleared during a transmission, the TxD signal becomes idle after the comple-
tion of the transmission in progress. Clearing and then setting the TE bit during a transmission
queues an idle character to be sent after the frame currently being transmitted.
The block diagram of the SCI receiver is shown in Figure 9.14. The SCI receiver can accom-
modate either 8-bit or 9-bit data characters. The state of the M bit in the SCI control register 1
determines the length of data characters. When receiving 9-bit data, the R8 bit of the SCI
x
DRH
register holds the ninth bit.
During an SCI reception, the receive shift register shifts in a frame from the RxD pin.
The SCI data register is the read-only buffer between the internal bus and the receive shift
register. After a complete frame is shifted into the receive shift register, the data portion of
the frame is transferred to the SCI data register. The receive data register full flag, RDRF, in
the SCI
x
SR1 register becomes set, indicating that the receive byte can be read. If the receive
interrupt enable bit RIE in the SCI
x
CR2 register is also set, then an interrupt is requested to
the MCU.
The receiver uses the method illustrated in Figure 9.5 to detect the arrival of the start bit
and uses the majority function of the samples RT8, RT9, and RT10 to determine the logic value
of a bit.
The SCI module supports the HCS12 to operate in a multiple-receiver system. When a
message is not intended for this MCU, the SCI module will put itself in a standby state to
ignore the rest of the message. This is done by setting the RWU bit of the SCI
x
CR2 register. In
the standby state, the SCI module will still load the receive data into the SCI
x
DRH/L registers,
but it will not set the RDRF flag.
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