Hardware Reference
In-Depth Information
7
6
5
4
3
2
1
0
Reset value
= 0x00
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
TDRE: transmit data register empty flag
0 = no byte was transferred to the transmit shift register.
1 = transmit data register is empty.
TC: transmit complete flag
0 = transmission in progress.
1 = no transmission in progress.
RDRF: receiver data register full flag
0 = SCI x DR empty.
1 = SCI
DR full.
IDLE: idle line detected flag
0 = RxD line active.
1 = RxD line becomes idle.
OR: overrun error flag
0 = no overrun.
1 = overrun detected.
NF: noise error flag
Set during the same cycle as the RDRF bit but not set in the case.
of an overrun (OR).
0 = no noise.
1 = noise.
FE: framing error flag
Set when a 0 is detected where a stop bit was expected.
0 = no framing error.
1 = framing error.
PF: parity error flag
0 = parity correct.
1 = incorrect parity detected.
x
Figure 9.12 SCI status register 1 (SCI0SR1/SCI1SR1)
7
6
5
4
3
2
1
0
Reset value
= 0x00
0
0
0
0
0
BK13
TXDIR
RAF
BK13: break transmit character length
0 = break character is 10- or 11-bit long.
1 = break character is 13- or 14-bit long.
TXDIR: transmit pin data direction in single-wire mode
0 = TxD pin to be used as an input in single-wire mode.
1 = TxD pin to be used as an output in single-wire mode.
RAF: receiver active flag
RAF is set when the receiver detects a logic 0 during the RT1 time
period of the start bit search. RAF is cleared when the receiver detects
an idle character.
0 = no reception in progress.
1 = reception in progress.
Figure 9.13 SCI status register 2 (SCI0SR2/SCISR2)
The TDRE bit in the SCI x SR1 register is cleared by reading the SCI x SR1 register and
followed by writing a byte into the SCI x DRL register. All status flags related to reception are
cleared by reading the SCI status register followed by reading the SCI x DRL register.
 
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