Timer Functions - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 425

of the resulting PWM output is controlled by the PPOLx bit of the corresponding low-order
8-bit channel as well.
Once concatenated mode is enabled, then enabling or disabling the corresponding 16-bit
PWM channel is controlled by the low-order PWMEx bit. In this case, the PWMEx bits of the
high-order bytes have no effect and their corresponding PWM outputs are disabled. In concat-
enated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low- or
high-order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be
made by a 16-bit access to maintain data coherency. Either left-aligned or center-aligned output
mode can be used in concatenated mode and is controlled by the low-order CAEx bit. The high-
order CAEx bit has no effect.

PWM B OUNDARY C ASES
Table 8.5 summarizes the boundary conditions for the PWM regardless of the output mode
(applicable to both the 8-bit and 16-bit PWM modes).

PWMDTYx PWMPERx PPOLx PWMx Output

$00 >$00 1 Always low

(indicates no duty)
$00 >$00 0 Always high

(indicates no duty)
xx

$00 1 1 Always high

(indicates no period)

xx $00 1 0 Always low

(indicates no period)

.5 PWMPERx xx 1 Always high

.5 PWMPERx xx 0 Always low

Note: 1. Counter 5 $00 and does not count.

Table 8.5 ■ PWM boundary cases

E MERGENCY PWM S HUTDOWN
The PWM system can be shut down under emergency conditions. The emergency shutdown
is controlled by the PWMSDN register. The contents of this register are shown in Figure 8.50.

Example 8.21
▼ Write an instruction sequence to program the PWM channel 0 to output a waveform with
50 percent duty cycle and 100-kHz frequency. Assume that the E-clock is 24 MHz.
Solution: To achieve the 50 percent duty cycle, 100-kHz PWM output, we use the following
parameters:
• Clock source prescale factor set to 2
• Clock A selected as the clock input to PWM channel 0