Hardware Reference
In-Depth Information
•
Left-aligned mode
•
The value 120 written into the PWMPER0 register (frequency is 24 MHz 4 120 4 2 5
100 kHz)
•
The value 60 written into the PWMDTY0 register
The following instruction sequence will perform the confi guration:
#include “c:\miniide\hcs12.inc”
. . .
movb
#0,PWMCLK
; select clock A as the clock source for PWM0
movb
#1,PWMPRCLK
; set clock A prescaler to 2
movb
#1,PWMPOL
; channel 0 output high at the start of the period
movb
#0,PWMCAE
; select left-aligned mode
movb
#$0C,PWMCTL
; 8-bit mode, stop PWM in wait and freeze mode
movb
#120,PWMPER0
; set period value
movb
#60,PWMDTY0
; set duty value
movb
#0,PWMCNT0
; reset the PWM0 counter
bset
PWMEN,PWME0
; enable PWM channel 0
▲
7
6
5
4
3
2
1
0
PWMRSTRT
PWM7IN
PWMIF
PWMIE
PWMLVL
0
PWM7INL
PWM7ENA
Reset:
0
0
0
0
0
0
0
0
PWMIF: PWM interrupt flag
0 = no change on PWM7IN input.
1 = change on PWM7IN input.
PWMIE: PWM interrupt enable
0 = PWM interrupt is disabled.
1 = PWM interrupt is enabled.
PWMRSTRT: PWM restart
The PWM can only be restarted if the PWM channel input 7 is de-asserted. After writing a logic 1 to
this bit, the PWM channels start running after the corresponding counter passes the next "counter == 0"
phase.
PWMLVL: PWM shutdown output level
0 = PWM outputs are forced to 0.
1 = PWM outputs are forced to 1.
PWM7IN: PWM channel 7 input status
This bit reflects the current status of the PWM7 pin.
PWM7INL: PWM shutdown active input level for channel 7
0 = active level is low.
1 = active level is high.
PWM7ENA: PWM emergency shutdown enable
If this bit is logic 1, the pin associated with channel 7 is forced to input and the emergency shutdown
feature is enabled. All the other bits in this register are meaningful only if PWM7ENA = 1.
0 = PWM emergency feature is disabled.
1 = PWM emergency feature is enabled.
Figure 8.50
■
PWM Shutdown register (PWMSDN)
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