Hardware Reference
In-Depth Information
PWM P
OLARITY
The
polarity
of a PWM waveform refers to the voltage level (high or low) that a PWM wave-
form starts with in each period. Each PWM channel has a polarity bit to allow starting a wave-
form cycle with a high or low level. This is shown in Figure 8.44 as a MUX select of either the
Q or Q output of the PWM output flip-flop. When the PPOLx bit is 0, the Q output is selected
and the PWM output will start with a low. Otherwise, the output Q is selected and the PWM
output starts with a high.
PWM P
ERIOD
AND
D
UTY
Dedicated period and duty registers exist for each channel and are double buffered so that
if they change while the channel is enabled, the change will not take effect until one of the fol-
lowing occurs:
•
The effective period ends.
•
The counter is written (counter is reset to $00).
•
The channel is disabled.
In this way, the output will always be either the old waveform or the new waveform, not some
variation in between. If the channel is not enabled, then writes to the period and duty registers
will go directly to the latches and the buffer. A change in duty or period can be forced into ef-
fect immediately by writing the new values to the duty and/or period registers and then writing
to the counter. This forces the counter to reset and the new duty and/or period values to be
latched.
PWM C
OUNTERS
Each channel has a dedicated 8-bit up-and-down counter that runs at the rate of the se-
lected clock source. The counter is compared to the duty and period registers in each clock
cycle. When the counter matches the duty register, the output flip-flop changes state, causing
the PWM waveform to also change state. A match between the PWM counter and the period
register behaves differently depending on what output mode is selected.
Any value written to the counter causes the counter to reset to $00 and start to count
up, both the duty and period registers to be loaded with values from their buffers, and the
output to change according to the polarity bit. When the channel is disabled, the counter
stops.
PWM W
AVEFORM
A
LIGNMENT
The PWM timer provides the choice of two types of outputs:
left aligned
and
center
aligned
. A left-aligned waveform has two line segments in each period whereas a center-
aligned waveform has three line segments in one period. They are selected with the CAEx bits
in the PWMCAE register. The contents of the PWMCAE register are shown in Figure 8.46. If
the CAEx bit is 0, the corresponding PWM output will be left aligned.
7
6
5
4
3
2
1
0
CAE7
CAE6
CAE5
CAE4
CAE3
CAE2
CAE1
CAE0
Reset:
0
0
0
0
0
0
0
0
CAEx: center-aligned enable bit for channel x
0 = PWM channel x output is left aligned.
1 = PWM channel x output is center aligned.
Figure 8.46
■
PWM Center Align Enable register (PWMCAE)
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