Hardware Reference
In-Depth Information
The block diagram of a PWM channel is shown in Figure 8.44. A PWM channel must be
enabled to work. It is enabled by setting a bit in the PWME register. The contents of the PWME
register are shown in Figure 8.45. There is an edge-synchronizing circuit (labeled as GATE in
Figure 8.44) to guarantee that the clock will only be enabled or disabled at an edge.
Clock
source
8-bit counter
GATE
PWMCNTx
From port PTP
data register
(Clock edge sync)
up/
down
8-bit compare =
M
U
X
T
M
U
X
Q
To pin
driver
PWMDTYx
R
Q
PPOLx
8-bit compare =
PWMPERx
Q
T
CAEx
R
Q
PWMEx
Figure 8.44
■
PWM channel block diagram
7
6
5
4
3
2
1
0
PWME7
PWME6
PWME5
PWME4
PWME3
PWME2
PWME1
PWME0
Reset:
0
0
0
0
0
0
0
0
PWMEx: PWM channel x enable
0 = PWM channel x disabled.
1 = PWM channel x enabled.
Figure 8.45
■
PWM Enable register (PWME)
There are four major properties in a PWM waveform: polarity, alignment, period, and duty cycle.
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