Hardware Reference
In-Depth Information
In Figure 8.39, clock A is an input to an 8-bit down counter. This down counter loads a
user-programmable scale value from the scale register (PWMSCLA). When the down counter is
decremented to 1, two things happen: A pulse is output and the 8-bit counter is reloaded. The
output signal from this circuit is further divided by 2. In other words, the clock SA is derived by
the following equation:
Clock SA
5
clock A/(2 * PWMSCLA)
When PWMSCLA equals $00, the PWMSCLA value is considered a full-scale value of 256.
Similarly,
Clock SB
5
clock B/(2 * PWMSCLB)
C
LOCK
S
ELECT
Each PWM channel has a choice of two clock signals to use as the clock source for that
channel. The clock source selection is done by the PWMCLK register. The contents of this reg-
ister are shown in Figure 8.42.
7
6
5
4
3
2
1
0
PCLK7
PCLK6
PCLK5
PCLK4
PCLK3
PCLK2
PCLK1
PCLK0
0
0
0
0
0
0
0
0
Reset:
PCLKx: PWM channel
x
clock select (
x
= 7, 6, 3, 2)
0 = clock B as the clock source
1 = clock SB as the clock source
PCLKy: PWM channel
y
clock select (
y
= 5, 4, 1, 0)
0 = clock A as the clock source
1 = clock SA as the clock source
Figure 8.42
■
PWM Clock Select register (PWMCLK)
The main part of the PWM module consists of the timers. Each of the PWM channels has
an 8-bit counter, an 8-bit period register, and an 8-bit duty cycle register.
The waveform output period is controlled by a match between the period register and the
value in the counter. The duty cycle is controlled by a match between the duty cycle register
and the counter value that causes the state of the output to change during the period. The start-
ing polarity of the output is selectable on a per-channel basis and is selected by programming
the PWMPOL register. The contents of the PWMPOL register are shown in Figure 8.43.
7
6
5
4
3
2
1
0
PPOL7
PPOL6
PPOL5
PPOL4
PPOL3
PPOL2
PPOL1
PPOL0
0
0
0
0
0
0
0
0
Reset:
PPOLx: PWM channel x polarity
0 = PWM channel x output is low at the start of a period, then goes high when the
duty count is reached.
1 = PWM channel x output is high at the start of a period, then goes low when the
duty count is reached.
Figure 8.43
■
PWM Polarity register (PWMPOL)
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