Timer Functions - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 419

Clock A and clock B are scaled values of the input clock. The possible values for clock A
and clock B are derived by dividing the E-clock by 1, 2, 4, 8, 16, 32, 64, and 128. The value se-
lected for clock A and clock B is determined by the PCKA2,PCKA0 and PCKB2,PCKB0 bits
in the PWMPRCLK register, respectively. The contents of the PWMCTL and PWMPRCLK reg-
isters are shown in Figure 8.40 and Figure 8.41, respectively. Tables 8.3 and 8.4 show the avail-
able prescale values for clock A and clock B.

7 6 5 4 3 2 1 0

0

CON67 CON45 CON23 CON01 PSWAI PFRZ 0

0 0 0 0 0 0 0 0

Reset:

CONjk: concatenate channels j and k ( j = 0, 2, 4, or 6; k = j + 1)

0 = channels j and k are separate 8-bit PWMs.
1 = channels j

becomes the high-order byte and channel k becomes the low-order byte. Channel

j and k are concatenated to create one 16-bit PWM channel. Channel

k output pin is used as the output for this 16-bit PWM. Channel k clock select bit

determines the clock source, channel polarity bit determines the polarity,

channel k enable bit enables the output,and channel k center-aligned enable bit
determines the output mode.
PSWAI: PWM stops in wait mode
0 = allow the clock to the prescaler to continue while in wait mode.
1 = stop the input clock to the prescaler whenever the MCU is in wait mode.
PFRZ: PWM counters stop in freeze mode
0 = allow PWM to continue while in freeze mode.
1 = disable PWM input clock to the prescaler whenever the part is in freeze mode.

k

Figure 8.40 ■ PWM Control register (PWMCTL)

7 6 5 4 3 2 1 0

0 PCKB2 PCKB1 PCKB0 0 PCKA2 PCKA1 PCKA0

Reset: 0 0 0 0 0 0 0 0

Figure 8.41 ■ PWM Prescale Clock Select register (PWMPRCLK)

Value of Clock
B

Value of Clock
A

PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

E-clock
E-clock/2
E-clock/4
E-clock/8
E-clock/16
E-clock/32
E-clock/64
E-clock/128

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

E - clock
E - clock/2
E - clock/4
E - clock/8
E - clock/16
E - clock/32
E - clock/64
E - clock/128

Table 8.3 ■ Clock B prescaler selects Table 8.4 ■ Clock A prescaler selects

C LOCK S CALE
The SA clock takes clock A as one of its inputs and divides it further with a user-programmable
value (from 1 to 256) and then divides it by 2. The SB clock is derived similarly, but with clock B as
its input.