Hardware Reference
In-Depth Information
L EFT -A LIGNED O UTPUT
In the left-aligned output mode, the 8-bit counter is configured as an up counter only. When
the PWM counter equals the duty register, the output flip-flop changes state; this causes the PWM
waveform to also change state. A match between the PWM counter and the period register resets the
counter and the output flip-flop. The counter counts from 0 to the value in the period register - 1.
The waveform of the left-aligned mode is shown in Figure 8.47. The frequency of the PWM
output is given by the following equation:
PWMx frequency 5 clock (A, B, SA, or SB) 4 PWMPERx
The duty cycle of the waveform depends on the selected polarity.
Polarity 5 0,
PWMx duty cycle 5 [( PWMPERx 2 PWMDTYx ) 4 PWMPERx ] 3 100%
Polarity 5 1,
PWMx duty cycle 5 [ PWMDTYx 4 PWMPERx ] 3 100%
PPOLx = 0
PPOLx = 1
PWMDTYx
Period = PWMPERx
Figure 8.47 PWM left-aligned output waveform
C ENTER -A LIGNED M ODE
In this mode, the 8-bit PWM counter operates as an up-and-down counter and is set to count
up whenever the counter is equal to $00. The counter compares with two registers, a duty reg-
ister and a period register, in each clock cycle. When the counter matches the duty register, the
output flip-flop changes state, causing the PWM waveform to also change state. A match between
the PWM counter and the period register changes the counter direction from an up count to a
down count. When the PWM counter decrements and matches the duty register again, the output
flip-flop changes state, causing the PWM output to also change state. When the PWM counter
decrements and reaches zero, the counter direction changes from a down count back to an up
count and the period and duty registers are reloaded from their buffers. Since the PWM counter
counts from 0 up to the value in the period register and then back down to 0, the effective period
is PWMPERx 3 2.
The output waveform of the center-aligned mode is shown in Figure 8.48. The frequency of
the center-aligned PWM output can be calculated using the following expression:
PWMx frequency 5 clock(A, B, SA, or SB) 4 (2 × PWMPERx )
The duty cycle of the waveform depends on the selected polarity.
Polarity 5 0,
PWMx duty cycle 5 [( PWMPERx 2 PWMDTYx ) 4 PWMPERx ] 3 100%
Polarity 5 1,
PWMx duty cycle 5 [ PWMDTYx 4 PWMPERx ] 3 100%
PWM 16- BIT F UNCTIONS
Two 8-bit PWM modules can be concatenated into one 16-bit PWM module. The concate-
nation of the PWM channels is controlled by the CON bits of the PWMCTL register. The 16-bit
mode PWM system is illustrated in Figure 8.49.
 
Search WWH ::




Custom Search