Timer Functions - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 412

8.9.3 The Operation of the Enhanced Input-Capture Function
The enhanced input-capture function has all the registers in the input-capture function of
the standard timer module. New registers are added to implement the additional features. An
input-capture register is empty if its value has been read or latched into its associated holding
register. A holding register is empty if its value has been read. An enhanced input-capture chan-
nel can be configured to operate in either latch mode or queue mode.
Figures 8.35 and 8.36 illustrate the registers related to the operation of the latch mode
and queue mode, respectively. In both diagrams, channels IC0 to IC3 are identical and IC4 to
IC7 are identical. Only one channel in each group is shown in the figure. The latch mode and
queue mode are selected by setting and clearing the LATQ bit of the ICSYS register (shown in
Figure 8.31).

÷1,2, . . . ,128 16-bit load register

÷1, 4, 8, 16

E-clock

Prescaler 16-bit free-running

main timer

16-bit modulus
down counter

E-clock

Prescaler

Comparator
TCx capture/compare
register

PTx Pin logic

Delay
counter

EDG x

One IC channel
(IC0:IC3)

TCxH hold register

ICLAT, LATQ, BUFEN
(force latch)

To other IC channels

Write $0000 to
modulus counter

LATQ
(MDC latch enable)

Comparator
TCx capture/compare
register

One IC channel
(IC4:IC7)

Pin logic

EDG i

PTi

MUX

EDG j
j

= 8 - i

Figure 8.35 ■ Enhanced input-capture function block diagram in latch mode