Timer Functions - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 413

16-bit load register

÷ 1,2, . . . ,128

÷ 1, 4, 8, 16

E clock Prescaler 16-bit free-running

main timer

16-bit modulus
down counter

E clock

Prescaler

Pin logic Comparator

TCx capture/compare
register

PTx

Delay
counter

EDG x

One IC channel
(IC0:IC3)

TCxH hold register

To other IC channels

Comparator
TCx capture/compare
register

One IC channel
(IC4:IC7)

Pin logic

EDG i

PTi

MUX

EDG j

= 8 - i j

Figure 8.36 ■ Enhanced input-capture function block diagram in queue mode (channels
IC0...IC3 block diagram)

In the latch mode, the latching function occurs when the modulus down counter reaches 0
or a zero is written into the count register MCCNT. With a latching event, the contents of the
IC registers and 8-bit pulse accumulators are transferred to their holding registers. After this,
the 8-bit pulse accumulators are cleared. In the queue mode, the main timer value is copied
into the IC register (TC x register) by a valid input pin transition. With a new occurrence of a
capture, the value of the IC register is transferred to its holding register and the IC register holds
the new timer value. The queue mode and latch mode can be entered only when the holding
registers are enabled; this can be done by setting the BUFEN bit of the ICSYS register.
The HCS12 is often used in noisy environments such as automotive applications. Due to
the noise, false signal edges often occur in input-capture pins. To distinguish between true edge
and false edge (usually very short), a delay counter is added to the enhanced input-capture func-
tion. Any detected edge with a duration shorter than the preprogrammed value is ignored. The
duration of the delay is controlled by the DLYCT register. The contents of the DLYCT register
are shown in Figure 8.37. If enabled, after detection of a valid edge on the input-capture pin, the
delay counter counts the preselected number of E-clock cycles; then it generates a pulse to latch
the TCNT value into the input-capture register (TC x ). The pulse is generated only if the level of