Hardware Reference
In-Depth Information
A 16-bit modulus down counter with 4-bit prescaler.
Four user-selectable delay counters for increasing input noise immunity.
8.9.1 Enhanced Capture Timer Modes of Operation
The enhanced capture timer has eight input-capture/output-compare (IC/OC) channels, the
same as on the HCS12 standard timer module. Four IC channels (IC7, . . . , IC4) are the same as the
standard timer with one capture register that memorizes the timer value captured by an action on
the associated input pin. Four other IC channels (IC3, . . . , IC0), in addition to the capture register,
also have one buffer, called the holding register . This permits the register to memorize two dif-
ferent timer values without generating any interrupt. This feature can reduce software overhead
in applications that require capturing two edges in order to perform further computation. In addi-
tion, the ECT module provides the option of preventing a captured value from being overwritten
before it was read or transferred to the holding register. This option is controlled by the Input
Control Overwrite (ICOVW) register. The contents of this register are shown in Figure 8.34. This
capability will be useful when external events occur at a rate that the CPU cannot read quickly
enough.
7
6
5
4
3
2
1
0
Reset value
= 0x00
NOVW7
NOVW6
NOVW5
NOVW4
NOVW3
NOVW2
NOVW1
NOVW0
NOVW
: no input-capture overwrite
0 = the contents of the related capture register or holding register can be overwritten
when a new input-capture or latch occurs.
1 = the related capture register or holding register cannot be written by an event
unless it is empty. This will prevent the captured value to be overwritten until it
n
is read or latched in the holding register.
Figure 8.34 Input Control Overwrite register (ICOVW)
Four 8-bit pulse accumulators are associated with the four IC buffered channels. Each pulse
accumulator has a holding register to memorize its value by an action on its external input.
Each pair of pulse accumulators can be used as a 16-bit pulse accumulator.
8.9.2 Why the Enhanced Capture Timer Module?
There are applications that require the capture of two consecutive edges (could be both ris-
ing or both falling, or one rising and the other falling) at very high frequencies. In Example 8.2,
the following instructions (faster than movw TCx,edge_ist by one E cycle) are executed before we
have time to wait for the arrival of the second edge (after we detect the first edge):
ldd TCx
std . . .
It takes fi ve E-clock cycles to execute these two instructions, which set the upper limit on the
signal frequency that can be dealt with. By providing the capability of setting the interrupt fl ag
(or interrupting the CPU) after two signal edges have been captured, the upper limit of the sig-
nal frequency that can be handled can be signifi cantly improved.
The input-capture function of the original standard timer module allows the newly captured
value to overwrite the old one even if the CPU has not read the old value yet. This can cause a
problem when the event frequency is very high. The enhanced input-capture function allows the
user to prevent the overwriting of captured values by enabling the nonoverwrite feature.
 
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