Advanced Parallel I/O - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 314

3. Port Data Direction register (DDRH, DDRJ, DDRP)
4. Port Reduced Drive register (RDRH, RDRJ, RDRP)
5. Port Pull Device Enable register (PERH, PERJ, PERP)
6. Port Polarity Select register (PPSH, PPSJ, PPSP)
7. Port Interrupt Enable register (PIEH, PIEJ, PIEP)
8. Port Interrupt Flag register (PIFH, PIFJ, PIFP)
All except the last two registers have their equivalents in Port T. The contents of the Port
H Interrupt Enable register and Port H Interrupt Flag register are shown in Figures 7.15 and
7.16, respectively.

7 6 5 4 3 2 1 0

Reset value
= 0x00

PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0

PIEH[7:0]: interrupt enable Port H
0 = interrupt is disabled.
1 = interrupt is enabled.

Figure 7.15 ■ Port H Interrupt Enable register (PIEH)

7 6 5 4 3 2 1 0

Reset value
= 0x00

PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0

PIFH[7:0]: interrupt flag Port H
0 = no active edge pending.
1 = active edge has occurred (writing a 1 clears the associated flag).

Figure 7.16 ■ Port H Interrupt Flag register (PIFH)

Port H is associated with two SPI modules. Port J is associated with the fifth CAN and the
I 2 C module. Port P is associated with the PWM and two SPI modules. In all modes, Port P pins
PP[7:0] can be used either for general-purpose I/O or with the PWM and SPI subsystems. The
pins are shared between the PWM channels and the SPI1 and SPI2 modules. If the PWM func-
tion is enabled, these pins become PWM output channels, with the exception of pin 7, which
can be PWM input or output. If SPI1 or SPI2 are enabled and PWM is disabled, the respective
pin configuration is determined by several status bits in the SPI module. Both Port H and Port P
have eight pins, whereas Port J has only four pins.
The interrupt enable as well as the sensitivity to rising or falling edges can be individu-
ally configured on a per-pin basis. If a pin's pull-down device is enabled, then the interrupt
is rising edge triggered. Otherwise, it is falling edge triggered. All 8 bits or pins of the port
share the same interrupt vector. Interrupts can be used with the pins configured as inputs or
outputs.
An interrupt is generated when a bit in the Port Interrupt Flag register and its
corresponding port interrupt enable bit are both set. This feature can be used to wake up
the CPU when it is in the stop or wait mode. Each Port P pin can also be used as an edge-
sensitive interrupt source. A digital filter on each pin prevents pulses shorter than a speci-
fied time from generating an interrupt. The minimum time varies over process conditions,
temperature, and voltage.