Hardware Reference
In-Depth Information
PH0/MISO1/KWH0
PH1/MOSI1/KWH1
PP0/MISO1/PWM0/KWP0
PP1/MOSI1/PWM1/KWP1
PH2/SCK1/KWH2
PP2/SCK1/PWM2/KWP2
PH3/SS1/KWH3
PP3/SS1/PWM3/KWP3
PH4/MISO2/KWH4
PJ0/KWJ0
PJ1/KWJ1
PP4/MISO2/PWM4/KWP4
PH5/MOSI2/KWH5
PP5/MOSI2/PWM5/KWP5
PH6/SCK2/KWH6
PJ6/KWJ6/RXCAN4/SDA/RXCAN0
PP6/SS2/PWM6/KWP6
PH7/SS2/KWH7
PJ7/KWJ7/TXCAN4/SCL/TXCAN0
PP7/SCK2/PWM7/KWP7
Figure 7.17
■
Port H pins and
their alternate functions
Figure 7.18
■
Port J pins and
their alternate functions
Figure 7.19
■
Port P pins and
their alternate functions
The functions of Port H, J, and P pins are shown in Figures 7.17, 7.18, and 7.19,
respectively.
Many HCS12 devices have implemented two 8-channel A/D converters (AD1 and AD0). For
those devices with a single 8-channel A/D converter, the module is referred to as AD instead
of AD0. These two ports are analog input interfaces to the analog-to-digital subsystem. When
analog-to-digital functions are not enabled, these two ports are available for general-purpose
I/O. Since these two ports cannot be used as output, there are no data direction registers associ-
ated with them.
The ports have no resistive input loads and no reduced drive controls. PTAD0 and PTAD1
are data registers of Port AD0 and AD1, respectively. Each A/D module has an ATD Digital
Input Enable register. In order to use an A/D pin as a digital input, its associated bit in this
register needs to be set to 1. The contents of this register are shown in Figure 7.20.
7
6
5
4
3
2
1
0
Reset value
= 0x00
IEN7
IEN6
IEN5
IEN4
IEN3
IEN2
IEN1
IEN0
IENx: ATD digital input enable on channel x
0 = disable digital input buffer to PTADx pin.
1 = enable digital input buffer to PTADx pin.
Figure 7.20
■
ATD Input Enable register (ATD0DIEN and ATD1DIEN)
This port is available in the HCS12's H subfamily. In addition to being a general I/O port,
Port L is connected to the LCD driver. The HCS12 H subfamily is designed to support LCD
interfacing and motor control. Port L has the following registers:
•
Port I/O register (PTL)
•
Port Data Direction register (DDRL)
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