Advanced Parallel I/O - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 313

Example 7.1
▼

Give an instruction to configure the MODRR register to achieve the following port
routing:
1. CAN0: use pins PM1 and PM0
2. CAN1: use pins PM3 and PM2
3. CAN2: use pins PM5 and PM4
4. CAN3: use pins PM7 and PM6
5. I 2 C: use PJ7 and PJ6
6. SPI0: use pins PS7,PS4
7. SPI1: use pins PH3,PH0
8. SPI2: use pins PH7,PH4

Solution: For this routing requirement, all we need to do is to prevent CAN4 from using any
port pins and keep the default routing after reset. The following instruction will satisfy the
requirement:
movb #$60,MODRR ; CAN4 must be disabled

▲

Example 7.2
▼ Give an instruction to configure the MODRR register to achieve the following port
routing:
1. CAN0: use pins PM1 and PM0
2. CAN1: use pins PM3 and PM2
3. CAN2: disabled
4. CAN3: disabled
5. I 2 C: use PJ7 and PJ6
6. SPI0: use pins PS7,PS4
7. SPI1: use pins PP3,PP0
8. SPI2: use pins PH7,PH4

Solution: This routing requirement can be satisfied by the following instruction:
movb #$40,MODRR ; CAN2 , CAN4 must be disabled

▲

7.5.7 Ports H, J, and P
These three I/O ports have the same set of registers associated with them. All of the pins
associated with these three ports have edge-triggered interrupt capability in the wired-OR fash-
ion. The SPI function pins can be routed to Ports H and P. The rerouting of SPI functions is done
by programming the MODRR register. Each of these three ports has eight associated registers.
1. Port I/O register (PTH, PTJ, PTP)
2. Port Input register (PTIH, PTIJ, PTIP)