Hardware Reference
In-Depth Information
7
6
5
4
3
2
1
0
0
0
0
WCOP
RSBCK
CR2
CR1
CR0
Reset:
0
1
0
0
0
0
0
0
WCOP: windowed COP mode bit
When set, a write to the ARMCOP register must occur in the last 25%
of the selected period. A write during the first 75% of the selected
period will reset the MCU.
0 = Normal COP operation.
1 = Windowed COP operation.
RSBCK: COP and RTI stop in active BDM mode bit
0 = Allows the COP and RTI to keep running in active BDM mode.
1 = Stops the COP and RTI whenever the HCS12 is in active BDM mode.
CR2:CR0: COP watchdog time rate select (number of OSCCLK cycles)
000: COP disabled
001: 2
14
010: 2
16
011: 2
18
100: 2
20
101: 2
22
110: 2
23
111: 2
24
Figure 6.17
■
CRG COP control register (COPCTL)
When a microcontroller is performing normal operations, power consumption is unavoid-
able. However, the microcontroller in an embedded system may not always be performing use-
ful operations. Under this situation, it would be ideal for the power consumption to be reduced
to the minimum. This issue is especially important for those embedded products powered by
batteries. The HCS12 has two low-power modes that can reduce power consumption dramati-
cally:
wait
and
stop
modes.
The wait mode is entered by executing the
wai
instruction. The wai instruction pushes all
CPU registers (except the stack pointer) and the return address onto the stack and enters a wait
state. During the wait state, CPU clocks are stopped (clock signals that drive the ALU and reg-
ister file), but other clocks in the microcontroller (clock signals that drive peripheral functions)
continue to run.
The CPU leaves the wait state when it senses one or more of the following events:
•
Maskable interrupts that are not masked
•
Nonmaskable interrupts
•
Resets
On leaving the wait state, the HCS12 CPU sets the appropriate interrupt mask bit(s), fetches
the vector corresponding to the exception sensed, and continues instruction execution at the
location the vector points to.
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