Hardware Reference
In-Depth Information
When the S bit in the CCR register is cleared and a
stop
instruction is executed, the HCS12
saves all CPU registers (except the stack pointer) in the stack, stops all system clocks, and puts
the microcontroller in
standby
mode. The standby operation minimizes the system power con-
sumption. The contents of registers and the states of I/O pins remain unchanged.
Asserting the RESET, XIRQ, or IRQ signal ends standby mode. If it is the XIRQ signal that
ends the stop mode and the X mask bit is 0, instruction execution resumes with a vector fetch
for the XIRQ interrupt. If the X mask bit is 1 (XIRQ disabled), a two-cycle recovery sequence is
used to adjust the instruction queue, and execution continues with the next instruction after
the
stop
instruction.
There are four possible sources of resets.
•
Power-on (POR) and low-voltage detector (LVD) reset
•
RESET pin
•
COP reset
•
Clock monitor reset
The COP and clock monitor resets have been discussed earlier. Power-on, low-voltage detector,
and RESET pin resets share the same reset vector. The COP reset and the clock monitor reset
each have a separate vector.
The HCS12 has a circuitry to detect when the
V
DD
supply to the MCU has reached a
certain level and asserts reset to the internal circuits. The detector circuit is triggered by the
slew rate. As soon as a power-on reset is triggered, the CRG module performs a quality check
on the incoming clock signal. Start of the reset sequence is delayed until the clock check in-
dicates a valid clock signal or the clock check was unsuccessful, and the CRG module enters
self-clock mode.
The HCS12 distinguishes between internal and external resets by sensing how quickly the
signal on the RESET pin rises to logic high after it has been asserted. When the HCS12 senses
any of the four reset conditions, internal circuitry drives the RESET pin low for 128 SYSCLK
cycles (this number might be increased by 3 to 6 SYSCLK cycles), then releases. Sixty-four SYS-
CLK cycles later, the CPU samples the state of the signal applied to the RESET pin. If the signal
is still low, an external reset has occurred. If the signal is high, the reset has been initiated in-
ternally by either the COP system or the clock monitor.
The power supply to an embedded system may drop below the required level. If the micro-
controller keeps working under this situation, the contents of the EEPROM might be corrupted.
The common solution is to pull the RESET signal to low so that the microcontroller cannot
execute instructions. A low-voltage-inhibit (LVI) circuit, such as the Freescale MC34064, can
be used to protect against the EEPROM corruption. Figure 6.18 shows an example of the reset
circuit with a manual reset and LVI circuit.
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