Interrupts, Clock Generation, Resets, and Operation Modes - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 292

DDRP 5 0xFF; // configure Port P for output

CRGINT | 5 RTIE; // enable RTI interrupt

asm( “CLI” ); // enable interrupt globally

while(1);

}

#pragma interrupt_handler rtiISR
void rtiISR(void) {

CRGFLG 5 0x80; // clear RTIF bit

PTB 5 segPat[seq 1 ix]; // output the segment pattern

PTP 5 digit[ix]; // output digit select value

ix 11 ; // increment digit index within a sequence

if (ix 55 4)

ix 5 0;

count 22 ; // decrement repetition count

if(count 55 0){ // if repetition count is 0, then change to the next sequence

seq 11 ;

count 5 400;

}

if(seq 55 10) // Reach the last sequence?

seq 5 0;

}

The required modification to this program for it to compile with the EGNU IDE is given in
Appendix E.

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6.8 Computer Operating Properly

The COP (a free-running watchdog timer) enables the user to find out if a user program is
running and sequencing properly. When the COP times out, it resets the CPU. The CPU reset
by the COP is an indication that the software is no longer being executed in the intended se-
quence. The software that utilizes the COP function must include an instruction sequence to
prevent the COP from timing out.
To prevent the COP module from resetting the MCU, one must write the value $55 fol-
lowed by $AA into the ARMCOP register. Other instructions can be inserted between the val-
ues $55 and $AA, but the sequence ($55, $AA) must be completed prior to the COP timeout
period to avoid a COP reset. Writing any value other than $55 or $AA into this register will
reset the MCU.
The functioning of the COP module and its timeout period are controlled by the COPCTL
register. The contents of this register are shown in Figure 6.17. The COP module is disabled
if the CR2:CR0 bits of this register are set to 000. The COP has a windowed option for its
operation. The windowed COP operation is enabled by setting the WCOP bit of the COPCTL
register. In this mode, writes to the ARMCOP register to clear the COP timer must occur in
the last 25 percent of the selected timeout period. A premature write will immediately reset
the MCU.