Interrupts, Clock Generation, Resets, and Operation Modes - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 284

7 6 5 4 3 2 1 0

CME PLLON AUTO ACQ 0 PRE PCE SCME

Reset: 0 0 0 0 0 0 0 0

CME: clock monitor enable bit
0 = Clock monitor is disabled.
1 = Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset
sequence or self-clock mode.
PLLON: phase-lock-loop on bit
0 = PLL is turned off.
1 = PLL is turned on. If AUTO bit is set, the PLL will lock automatically.
AUTO: automatic bandwidth control bit
0 = Automatic mode control is disabled and the PLL is under software control, using
ACQ bit.
1 = High-bandwidth filter is selected.
ACQ: acquisition bit (if AUTO bit = 1, this bit has no effect)
0 = Low-bandwidth filter is selected.
1 = High-bandwidth filter is selected.
PRE: RTI enable during pseudo-stop bit
0 = RTI stops running during pseudo-stop mode.
1 = RTI continues running during pseudo-stop mode.
PCE: COP enable during pseudo-stop bit
0 = COP stops running during pseudo-stop mode.
1 = COP continues running during pseudo-stop mode.
SCME: self-clock mode enable bit
0 = Detection of crystal clock failure causes clock monitor reset.
1 = Detection of crystal clock failure forces the MCU in select-clock mode.

Figure 6.14 ■ The CRG PLL control register (PLLCTL)

2. After turning on the PLL, wait for a given time ( t acq ) before entering tracking mode
(clear ACQ to 0). The parameter t acq can be found in the HCS12DP256 block user guide.
3. After entering the tracking mode, wait for t al ns before selecting the PLLCLK signal
as the source for system and core clocks (by setting the PLLSEL bit of the PLLCTL
register to 1).

6.6.5 System Clock Generation
The clock generator is illustrated in Figure 6.15. This circuit generates the system and core
clocks used in the microcontroller. When dealing with external memory or peripheral modules,
the bus clock, referred to as E-clock in this topic, is used. The E-clock is derived by dividing the
SYSCLK clock by 2. If the PLLCLK is chosen to be the SYSCLK, then the frequency of the E-
clock is half that of PLLCLK.
When the MCU enters the self-clock mode, the oscillator clock source is switched to the
PLLCLK running at its minimum frequency, f SCM .
Either the oscillator output OSCCLK (when PLLSEL 5 0) or the PLL output PLLCLK
(PLLSEL 5 1) can be selected as SYSCLK. The oscillator can be completely bypassed and turned
off by selecting an external clock source instead. The clock monitor, PLL, RTI, COP, and all
clock signals based on OSCCLK are driven by this external clock instead of the output of the
oscillator. As Figure 6.15 shows, SYSCLK can be a buffered version of the external clock input
and the E-clock can be derived by dividing the external clock by 2.