Hardware Reference
In-Depth Information
7
6
5
4
3
2
1
0
R
0
0
LOCKIE
0
0
S
0
Reset:
0
0
0
0
0
0
0
0
RTIE: Real-time interrupt enable bit
0 = Interrupt requests from RTI are disabled.
1 = Interrupt requests from RTI are enabled.
LOCKIE: Lock interrupt enable bit
0 = LOCK interrupt requests are disabled.
1 = LOCK interrupt requests are enabled.
SCMIE: Self-clock mode interrupt enable bit
0 = SCM interrupt requests are disabled.
1 = Interrupt will be requested whenever the SCMIF bit is set.
Figure 6.11
■
The CRG interrupt enable register (CRGINT)
7
6
5
4
3
2
1
0
RTIF
PORF
0
LOCKIF
LOCK
TRACK
SCMIF
SCM
Reset:
0
0
0
0
0
0
0
0
RTIF: real-time interrupt flag
The RTIF flag is set to 1 at the end of the RTI period. This flag can only be cleared by
writing a 1 to it. When the RTIE bit is 1, the setting of this bit will cause an interrupt.
0 = RTI time-out has not occurred.
1 = RTI time-out has occurred.
PORF: power-on reset flag
This flag is set to 1 when a power-on reset occurs. It can only be cleared by writing a
1 to it.
0 = Power-on reset has not occurred.
1 = Power-on reset has occurred.
LOCKIF: PLL lock interrupt flag
This flag is set to 1 when the LOCK status bit changes. This flag can only be cleared
by writing a 1 to it.
0 = No change in the LOCK bit.
1 = The LOCK bit has changed.
LOCK: lock status bit
This bit reflects the current state of PLL lock condition. This bit is cleared in self-clock
mode.
0 = PLL VCO is not within the desired tolerance of the target frequency.
1 = PLL VCO is within the desired tolerance of the target frequency.
TRACK: track status bit
This bit reflects the current state of PLL lock condition. This bit is cleared in self-clock
mode.
0 = Acquisition mode status.
1 = Tracking mode status.
SCMIF: self-clock mode interrupt flag
This bit is set to 1 when the SCM status bit changes. This flag can only be cleared by
writing a 1 to it.
0 = No change in SCM bit.
1 = SCM bit has changed.
SCM: self-clock mode status bit
SCM reflects the current clocking mode.
0 = MCU is operating normally with OSCCLK available.
1 = MCU is operating in self-clock mode with OSCCLK in an unknown state. All
clocks are derived from PLLCLK running at its minimum frequency,
f
SCM*
.
Figure 6.12
■
The CRG flag register (CRGFLG)
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