Interrupts, Clock Generation, Resets, and Operation Modes - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 281

Reference

XTAL

Lock

REFDV<3:0>

Lock
detector

Feedback

Reduced
consumption
oscillator

OSCCLK

Reference
programmable
divider

Up

Pdet
phase
detector

CPUMP VCO

Dow n

EXTAL

VDDPLL

Crystal
monitor

Loop
programmable
divider

Loop
filter

XFC
pin

PLLCLK

SYNR<5:0>

Figure 6.10 ■ PLL functional diagram

PLL O PERATION
In Figure 6.10, the OSCCLK clock is fed through the reference programmable divider and is
divided into a range from 1 to 16 (REFDV 1 1) to output the reference clock. The VCO output
clock (PLLCLK) is fed back through the programmable loop divider and is in a range of 2 to 128
in increments of [2 3 (SYNR 1 1)] to output the feedback clock.
The phase detector then compares the feedback clock with the reference clock. Correction
pulses are generated on the basis of the phase difference between these two signals. The loop fil-
ter then slightly alters the DC voltage on the external filter capacitor connected to the XFC pin
on the basis of the width and direction of the correction pulse. The filter can make fast or slow
corrections depending on its mode. The values of the external filter network and the reference
frequency determine the speed of the corrections and the stability of the PLL.

A CQUISITION AND T RACKING M ODES
The lock detector compares the frequencies of the feedback clock and the reference clock.
Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The
circuit determines the mode of the PLL and the lock condition on the basis of this comparison.
The PLL filter can be manually or automatically configured into one of two possible operat-
ing modes: acquisition mode and tracking mode. In acquisition mode, the filter can make large
frequency corrections to the Voltage Controlled Output (VCO) circuit. This mode is used at
PLL startup or when the PLL has suffered a severe noise hit and the VCO frequency is far off the
desired frequency. In tracking mode, the filter makes only small corrections to the frequency of
the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower.
The PLL enters tracking mode when the VCO frequency is nearly correct.
The operation of the PLL is controlled by four registers: CRGINT, CRGFLG, CLKSEL, and
PLLCTL. The contents of these four registers are shown in Figures 6.11, 6.12, 6.13, and 6.14.
The CRG interrupt register (CRGINT) enables or disables the interrupts associated with
the CRG module. The CRG Flag Register (CRGFLG) holds the status flags of the CRG module.
The CLKSEL register selects the clock source for the PLL. The PLLCTL register provides the
overall control to the PLL module.