Interrupts, Clock Generation, Resets, and Operation Modes - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 278

The phase-locked-loop (PLL) is a circuit technique that can accept a low-frequency clock
signal and produce a high-frequency clock output. In addition, the PLL has a feedback cir-
cuitry to stabilize the frequency of its output signal. The PLL has two operation modes:
acquisition mode and tracking mode . When the PLL is first powered up, the frequency of its
output is far from its target frequency . During this period, the PLL is in acquisition mode in
which the PLL can make large adjustments to quickly reach the target frequency. After the
PLL has attained its target output frequency, it enters tracking mode, in which it makes only
small adjustments so as not to deviate from the target frequency. This mode is useful when
the incoming clock signals (square waveform) deviate slightly because the frequency of the
crystal oscillator output may change slightly due to a change in temperature, humidity, or
barometric pressure.
6.6.1 Modes of CRG Operation
The CRG block can operate in one of the following four modes:
• Run mode . All functional parts of the CRG block are running in this mode.
• Wait mode . This mode allows the user to disable the system and core clocks by
programming the individual bits in the CLKSEL register.
• Stop mode . Depending on the setting of the PSTP bit of the CLKSEL register, stop
mode can be differentiated between full-stop (PSTP 5 0) and pseudo-stop mode
(PSTP 5 1). In full-stop mode, the oscillator is disabled, and thus all system and
core clocks are stopped. In pseudo-stop mode, the oscillator continues to run and
most of the system and core clocks are stopped. If the respective enable bits are set,
the COP and Real-Time Interrupt (RTI) modules will continue to run.
• Self-clock mode. This mode is entered if both the clock monitor enable bit (the
CME bit of the PLLCTL register) and the self-clock mode enable bit (the SCME bit
of PLLCTL) are set and the clock monitor detects a loss of clock (external oscillator
or crystal). As soon as the self-clock mode is entered, the CRG starts to perform
a clock quality check. The self-clock mode remains active until the clock check
indicates that the required quality (frequency and amplitude) of the incoming
clock signal is met. The self-clock mode should be used for safety purposes only. It
provides reduced functionality to the microcontroller (MCU) in case a loss of clock
is causing severe system conditions.
6.6.2 CRG Signals
• VDDPLL and VSSPLL . The PLL is a critical component for deriving a clock signal
with stable frequency. These two pins provide the operating voltage (VDDPLL) and
ground (VSSPLL) for the PLL circuitry and allow the supply voltage to the PLL to be
independent of the power supply to the rest of the circuit.
• XFC . A passive external loop filter must be placed on the XFC pin. The filter is a
second-order, low-pass filter to eliminate the VCO input ripple. The value of the
external filter network and the reference frequency determine the speed of the
corrections and the stability of the PLL. If the PLL usage is not required, the XFC
pin must be tied to VDDPLL. The PLL loop filter connection recommended by
Freescale is shown in Figure 6.5.
• EXTAL and XTAL . These two pins allow the user to connect an external crystal
oscillator or a CMOS compatible clock to control the internal clock generator
circuitry. The circuit connection for an external crystal oscillator is shown in