Interrupts, Clock Generation, Resets, and Operation Modes - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 277

asm(“cli”); // enable interrupt globally

while(1); // wait for interrupt forever

}
void INTERRUPT IRQISR(void)
{

cnt 11 ; // increment the count value

PTB

5 cnt;

// display the count value on LEDs

}.

6.6 Clock and Reset Generation Block (CRG)

This block is responsible for generating the clock signals required by the HCS12 instruc-
tion execution and all peripheral operations and providing default values for all on-chip regis-
ters. The block diagram of a CRG is shown in Figure 6.4.
A microcontroller needs a clock signal to operate. The clock signal has the waveform of
a square wave. Most people use a crystal oscillator to generate the clock signal. However, the
output of a crystal oscillator is a sinusoidal waveform that cannot be used to drive digital cir-
cuitry directly. Most microcontrollers and microprocessors have an on-chip oscillator to square
up the incoming sinusoidal waveform so that it can be used as the clock signal. Many crystal
oscillators also include the circuitry to square up the sinusoidal waveform. The on-chip oscilla-
tor circuitry can be bypassed for this type of crystal oscillator (also called external oscillators in
Freescale literature).

Power-on
reset

VREG

CRG

Clock and reset
control
Reset
generator

System
reset

RESET

CM fa il

Clock
monitor

XCLKS
EXTAL

Clock quality
checker

E-Clock

XTAL

OSC

Core clock

COP RTI

OSCCLK

Oscillator
clock

Registers

XFC
VDDPLL
VSSPLL

PLLCLK

PLL

Figure 6.4 ■ Block diagram of CRG