Hardware Reference
In-Depth Information
VDDPLL
C S
C P
HCS12
R S
XFC
Figure 6.5 PLL loop filter connections
C DC *
V DD
EXTAL
Crystal or
ceramic resonator
C 1
HCS12
XCLKS
XTAL
C 2
VSSPLL
Figure 6.6 Common crystal connections
CMOS compatible
external oscillator
(VDDPLL level)
EXTAL
HCS12
XCLKS
XTAL
Not connected
Figure 6.7 External oscillator connections
Figure 6.6; the circuit connection that uses a CMOS compatible external clock is
shown in Figure 6.7.
RESET . This pin is an active low, bidirectional reset pin. As an input, this signal
initializes the microcontroller to a known state. As an output, it indicates that a
system reset (internal to MCU) has been triggered.
XCLKS . This signal is an input that controls whether a crystal in combination with
the internal oscillator or an external clock source on the EXTAL pin (oscillator
circuitry is bypassed) is used to provide the clock signal required for the MCU
operation. The XCLKS signal is sampled on the rising edge of RESET . When this
signal is high, the crystal and the internal oscillator provide the OSC_CLK signal.
When this signal is low, the external clock provides the OSC_CLK signal.
 
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