Interrupts, Clock Generation, Resets, and Operation Modes - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 268

HPRIO Value to
Elevate
to Highest I Bit

Vector
Address

Vector
Number

CCR
Mask

Interrupt Source Local Enable

$FFFE
$FFFC
$FFFA
$FFF8
$FFF6
$FFF4
$FFF2
$FFF0
$FFEE
$FFEC
$FFEA
$FFE8
$FFE6
$FFE4
$FFE2
$FFE0
$FFDE
$FFDC
$FFDA
$FFD8
$FFD6
$FFD4
$FFD2
$FFD0
$FFCE
$FFCC
$FFCA
$FFC8
$FFC6
$FFC4
$FFC2
$FFC0
$FFBE
$FFBC
$FFBA
$FFB8
$FFB6
$FFB4
$FFB2
$FFB0
$FFAE
$FFAC
$FFAA
$FFA8
$FFA6
$FFA4
$FFA2
$FFA0
$FF9E
$FF9C
$FF9A
$FF98
$FF96
$FF94
$FF92
$FF90
$FF8E
$FF8C

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57

Reset
Clock monitor failure reset
COP failure reset
Unimplemented instruction trap
swi
XIRQ
IRQ
Real-time interrupt
Enhanced capture timer channel 0
Enhanced capture timer channel 1
Enhanced capture timer channel 2
Enhanced capture timer channel 3
Enhanced capture timer channel 4
Enhanced capture timer channel 5
Enhanced capture timer channel 6
Enhanced capture timer channel 7
Enhanced capture timer overflow
Pulse accumulator A overflow
Pulse accumulator A input edge
SPI0
SCI0
SCI1
ATD0
ATD1
Port J
Port H
Modulus down counter underflow
Pulse accumulator B overflow
CRG PLL lock
CRG self-clock mode
BDLC
IIC Bus
SPI1
SPI2
EEPROM
Flash
CAN0 wake-up
CAN0 errors
CAN0 receive
CAN0 transmit
CAN1 wake-up
CAN1 errors
CAN1 receive
CAN1 transmit
CAN2 wake-up
CAN2 errors
CAN2 receive
CAN2 transmit
CAN3 wake-up
CAN3 errors
CAN3 receive
CAN3 transmit
CAN4 wake-up
CAN4 errors
CAN4 receive
CAN4 transmit
Port P interrupt
PWM emergency shutdown

none
none
none
none
none
X bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit

none
PLLCTL(CME, SCME)
COP rate select
none
none
none
IRQCR(IRQEN)
CRGINT(RTIE)
TIE(C0I)
TIE(C1I)
TIE(C2I)
TIE(C3I)
TIE(C4I)
TIE(C5I)
TIE(C6I)
TIE(C7I)
TSCR2(TOI)
PACTL(PAOVI)
PACTL(PAI)
SP0CR1(SPIE, SPTIE)
SC0CR2(TIE,TCIE,RIE,ILIE)
SC1CR2(TIE,TCIE,RIE,ILIE)
ATD0CTL2(ASCIE)
ATD1CTL2(ASCIE)
PTJIF(PTJIE)
PTHIF(PTHIE)
MCCTL(MCZI)
PBCTL(PBOVI)
CRGINT(LOCKIE)
CRGINT(SCMIE)
DLCBCR1(IE)
IBCR(IBIE)
SP1CR1(SPIE, SPTIE)
SP2CR2(SPIE, SPTIE)
EECTL(CCIE, CBEIE)
FCTL(CCIE, CBEIE)
CAN0RIER(WUPIE)
CAN0RIER(CSCIE, OVRIE)
CAN0RIER(RXFIE)
CAN0TIER(TXEIE2-TXEIE0)
CAN1RIER(WUPIE)
CAN1RIER(CSCIE, OVRIE)
CAN1RIER(RXFIE)
CAN1TIER(TXEIE2-TXEIE0)
CAN2RIER(WUPIE)
CAN2RIER(CSCIE, OVRIE)
CAN2RIER(RXFIE)
CAN2TIER(TXEIE2-TXEIE0)
CAN3RIER(WUPIE)
CAN3RIER(CSCIE, OVRIE)
CAN3RIER(RXFIE)
CAN3TIER(TXEIE2-TXEIE0)
CAN4RIER(WUPIE)
CAN4RIER(CSCIE, OVRIE)
CAN4RIER(RXFIE)
CAN4TIER(TXEIE2-TXEIE0)
PTPIF(PTPIE)
PWMSDN(PWMIE)

-
-
-
-
-
-
$F2
$F0
$EE
$EC
$EA
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
$D6
$D4
$D2
$D0
$CE
$CC
$CA
$C8
$C6
$C4
$C2
$C0
$BE
$BC
$BA
$B8
$B6
$B4
$B2
$B0
$AE
$AC
$AA
$A8
$A6
$A4
$A2
$A0
$9E
$9C
$9A
$98
$96
$94
$92
$90
$8E
$8C

Table 6.1 ■ Interrupt vector map