Hardware Reference
In-Depth Information
There are at least two types of resets in each microprocessor: the
power-on reset
and the
manual reset.
A power-on reset allows the microprocessor to establish the initial values of reg-
isters and flip-flops and to initialize all I/O interface chips when power to the microprocessor
is turned on. A manual reset without power-down allows the computer to get out of most error
conditions (if hardware hasn't failed) and reestablish the initial conditions. The computer will
reboot
itself after a reset.
The starting address of the reset service routine either is a fixed value or is stored at a fixed
location (for HCS12). The reset service routine is stored in the read-only memory of all micro-
processors so that it is always ready for execution. At the end of the service routine, control
should be transferred to either the monitor program or the operating system.
Like nonmaskable interrupts, resets are also nonmaskable. However, resets are different
from the nonmaskable interrupts in that no registers are saved by resets because resets estab-
lish the values of registers.
The HCS12 exceptions can be classified into the following categories:
•
Maskable interrupts.
These include the IRQ pin interrupt and all peripheral
function interrupts. Since different HCS12 members implement a different number
of peripheral functions, they have different numbers of maskable interrupts.
•
Nonmaskable interrupts.
These include the XIRQ pin interrupt, the swi instruction
interrupt, and the unimplemented opcode trap.
•
Resets.
These include the power-on reset, the RESET pin manual reset, the
COP (computer operating properly) reset, and the clock monitor reset. For other
microcontrollers, the COP reset is also called the
watchdog
reset.
Since different HCS12 members implement a different number of peripheral functions,
they have a different number of maskable interrupts. The I flag in the CCR register is the global
mask of all maskable interrupts. Whenever the I flag is 1, all maskable interrupts are disabled.
All maskable interrupts have a local enable bit that allows them to be selectively enabled. They
are disabled (I flag is set to 1) when the HCS12 gets out of the reset state.
As with any other microcontroller, all HCS12 exceptions are prioritized. The priorities of
resets and nonmaskable interrupts are not programmable. However, we can raise one of the
maskable interrupts to the highest level within the group of maskable interrupts so that it can
get quicker attention from the CPU. The relative priorities of the other sources remain the same.
The bits 7 to 1 of the HPRIO register select the maskable interrupt at the highest priority within
the group of maskable interrupts. The contents of the HPRIO register are shown in Figure 6.1.
7
6
5
4
3
2
1
0
0
$001F
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
Figure 6.1
■
Highest-priority I interrupt register
The priorities and vector addresses of all HCS12 exceptions are listed in Table 6.1. The vec-
tor number column specifies the order of a specific interrupt source in the table. It is provided
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