Low-Power 60-GHz CMOS Radios for Miniature Wireless Sensor Network Applications - Ultra-Wideband and 60 GHz Communications for Biomedical Applications - page 198

Fig. 17 Tuning range of the
voltage-controlled oscillator
(VCO) in the frequency-
locked loop (FLL)

Fig. 18 Output spectrum of
the frequency-locked loop
(FLL) in 10-MHz span

pad through a dummy PA. In this way, we can monitor the FLL output frequency.
However, the absolute output power is not available through direct measurement
because of an extra 500

m routing that is necessary for the on-chip probing pads
setup. The simulated FLL output frequency and power are 60.12 GHz and

μ

3.6
dBm, respectively. The measured power consumption of the VCO core, buffers, and
PA are 8.8, 2.6, and 16.0 mW, respectively.
The envelope detectors sense the magnitude of the standing wave on the antenna,
and down-convert the signal from 60 GHz to direct current (DC). An active envelope
detector topology is used for larger output voltage levels, which is a class-AB biased
amplifier with parallel resistor-capacitor (RC) load at the output [ 35 ]. The bias of
the two envelope detectors is critical, and the connection through the patch antenna
ensures the DC voltage at both gates of the envelope detectors are the same. The
setup also makes sure that the patch antenna is not DC floating when it is operating.
Moreover, large devices are used and they are laid out in close proximity to lower
the mismatch between the two envelope detectors [ 34 ]. The simulated offset voltage
of the envelope detector inputs due to process variation is 190

−

V, corresponding to
a frequency offset of roughly 6 MHz (100 ppm). By changing the bias gate voltage
and the drain current, the input node of the envelope detectors can be designed as
high-impedance nodes, so that the two taps on the edge of the patch antenna do not
significantly affect the standing wave pattern. The measured power consumption of
one envelope detector is 670

μ

μ W.