Low-Power 60-GHz CMOS Radios for Miniature Wireless Sensor Network Applications - Ultra-Wideband and 60 GHz Communications for Biomedical Applications - page 199

Fig. 19 Frequency distribution of the frequency-locked loop (FLL) in different modes

The error amplifier provides the difference and controller gain for the FLL. It is
an amplifier with a differential input and an active load for single-ended output. Gain
of 20 dB and bandwidth of 300-MHz bandwidth is obtained from this stage. The
simulated offset voltage at the input of the error amplifier is 52

V, corresponding
to a frequency offset of roughly 11 MHz. The integrator introduces a pole at DC,
minimizing the steady state error between the FLL output and the natural resonant
frequency of the patch antenna. Bias conditions of the error amplifier, envelope detec-
tors, and the integrator must be considered together for the proper input voltage range
and gain margin. The loop filter stabilizes the FLL and is realized by a distributed
resistive transmission line with metal comb capacitor units with a self-resonant fre-
quency above 60 GHz. The cutoff frequency of the loop filter is designed to be 100
MHz.

μ

Measurement Results and Summary

The FLL is fabricated in a 130-nm CMOS process and the power consumption
(excluding the dummy PA to test pads) is 29.6 mW. Figure 17 shows the tuning
range of the VCO in the FLL, which covers ± 3 σ of the patch antenna resonant

frequency.
The output spectrum measured with a 10-MHz span while the FLL is locked is
shown in Fig. 18 . The locked frequency is at 59.27 GHz, which is within the variation
of the replica antenna. There are no reference spurs in the output spectrum, which
would typically appear in a frequency synthesizer with a crystal reference multiplied
by a PLL [ 36 ]. Fifteen FLLs from a single wafer were tested, and Fig. 19 compares