Cryptography Reference
In-Depth Information
is,
n
values. When the parity check mode is the compact one, the accumulation
of the messages of the
n
variables in each VNP must be memorized, that is,
n
memories if we update them immediately, and
2
n
in the opposite case. The
reasoning is the same if the VNPs are in compact mode and the PNPs are in
distributed mode, but in this case, it is the accumulations of messages in the
m
parities that must be memorized.
It is sometimes possible, as we shall see later, to memorize the
Z
j,p
messages
in a compressed way. The number of messages to memorize then passes from
B
to
g
(
B, d
c
)
,with
g
representing a compression function (
g
(
B, d
c
)
<B
)
.
9.2.5 Example of synthesis of an LDPC decoder architec-
ture
The two examples described in this part allow us to show two LDPC decoder
architectures using two different schedules. For each of these examples, we will
give the values of the parameters characterizing these architectures.
Parameters
Values
(
α
p
=1
,
α
v
=
d
v
=3
,
P
=3
)
Message propagation architecture
Position of the interconnection network
1
Control
Distributed, delayed update
VNP
Data path
Total sum, serial
Control
Compact
PNP
Data path
Trellis, parallel
Table 9.5 - Parameters characterizing the flooding schedule architecture.
Flooding schedule (according to parities)
The architecture described here to illustrate the flooding schedule is based on the
one proposed initially by Boutillon
et al.
[9.8]. It is schematized in Figure 9.15.
In this example,
P
=3
PNP operate simultaneously in compact mode. As
α
p
=1
and
α
v
=3
, there are 12 VNPs that operate simultaneously but in
distributed mode (only one VNP and one PNP are shown in the figure). Note
that the computing power of such an architecture is 12 branches per cycle.
The architecture of the PNPs is of the trellis type, with parallel implemen-
tation. The chronogram at the bottom of Figure 9.15 indicates that at time
T
1
,
d
v
=4
messages
L
j,p
(
T
1
)
are produced at each PNP. After a latency of
T
2
−
T
1
clock cycles, the
Z
j,p
(
T
2
)
messages leaving are sent to the VNPs. This operation
is reproduced
m/P
times to carry out one complete iteration. The data path of
the VNPs is of the total sum type, with a serial implementation. The delayed
update is shown by using two memory blocks, one for the extrinsic information
during accumulation (Lacc), and another for the total extrinsic information of
