Cryptography Reference
In-Depth Information
VNP
distributed
Delayed
update
Compact
Immediate
update
Flooding
Flooding
(parity)
Interleaving
(horizontal)
Compact
Delayed
update
Flooding
(variable)
PNP
distributed
Branches
Immediate
update
interleaving
(vertical)
Table 9.3 - Schedules associated with the different combinations of the node processor
controls.
schedules converge towards the same values: They do not change the information
propagation operation.
When one of the two types of processor is controlled in compact mode and
the other in distributed mode with immediate update, we implement a schedule
of the horizontal or vertical interleaving ( shue ) type. The order in which
the processors are activated is similar to the flooding schedule according to the
variables or the parities. Only the update of information changes since it is
performed as soon as a new input has arrived, thus accelerating the convergence
of the code.
The case where the two VNP and PNP processors are controlled in dis-
tributed mode is not of great interest. It would in fact correspond to controlling
the decoding, branch by branch.
The memory required to implement these different combinations is given in
Table 9.4.
VNP
Distributed
Delayed
update
Compact
Immediate
update
Compact
B + n
3 n + g ( B,d c )
2 n + g ( B,d c )
Delayed
update
B
+
n
+2
m
3
n
+2
m
+
B
2
n
+2
m
+
B
PNP
Distributed
Immediate
update
B + n + m
3 n + m + B
2 n + m + B
Table 9.4 - Quantity of memory necessary as a function of the combinations of the
different node processor controls.
Parameter B designates, like above, the number of branches in the graph.
Each extrinsic branch information must be memorized, whatever the schedule
used. In all cases the intrinsic variable information must also be memorized, that
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