Cryptography Reference
In-Depth Information
Figure 9.15 - Example of architecture for a flooding schedule (according to parities).
the previous iteration (Lold). At the end of each iteration, the role of these two
memories is exchanged. In this architecture, the extrinsic branch information
Z
j,p
can be saved either on the VNP side (solid line in the figure) or on the PNP
side (dotted line in the figure), like in the Chen
et al.
[9.12] and Guilloud
et al.
[9.24] architectures.
Horizontal interleaving schedule
This second type of architecture illustrates the horizontal interleaving schedule,
proposed by Mansour
et al.
[9.41] in a particular case of the turbo decoding
of LDPC codes. In this example, illustrated in Figure 9.16, there are
P
=3
PNPs that operate simultaneously in compact mode. As
α
p
=4
and
α
v
=3
,
there are 3 VNPs that operate simultaneously in distributed mode, which gives
a computing power of 3 branches per cycle.
