Hardware Reference
In-Depth Information
Figure 5.5
Another parity detector. (a) Circuit ports. (b) Illustrative time behavior. (c) State transition
diagram.
the arrangement in i gure 5.4c, based on the material seen in section 3.11; when the
reset pulse goes up (which subsequently resets the FSM), it causes the value of
y
to be
stored in the auxiliary register, producing
y_reg
, which stays stable (constant) until a
new calculation is completed (i.e., a new reset pulse occurs).
A slightly different parity detection problem is depicted in i gure 5.5, which has
to be reset only at power-up (thus a more usual situation). A data-valid (
dv
) bit indi-
cates the extension of the data vector whose parity must be calculated (when
dv
goes
up, a new vector begins, i nishing when
dv
returns to zero). It is assumed that after a
calculation (data stream) is completed, the machine must keep displaying the i nal
parity value until a new vector is presented, as depicted in the illustrative timing
diagram of i gure 5.5b, which shows two vectors of size 5 bits each, with i nal parity
y
= '1' for vector 1 and
y
= '0' for vector 2.
A Moore machine that complies with these specii cations is presented in i gure 5.5c
(note that in this example
dv
and
x
are updated at the negative clock edge). Because
of
dv
, this machine does not need to be reset before a new calculation starts. Indeed,
depending on the encoding scheme (sequential or Gray, for example), this circuit
might not need a reset signal at all because deadlock cannot occur (the unused code-
word will converge back to one of the machines' states) and
dv
will cause the compu-
tations to be correct even if the initial state is arbitrary (see exercise 3.11).
5.4.3 Basic One-Shot Circuit
One-shot circuits are circuits that, when triggered, generate a single voltage or current
pulse, possibly with a i xed time duration. This section discusses the particular case
in which the time duration of the output is exactly one clock period. In this example
it will be considered that the input lasts at least one clock period; generic cases are
studied in sections 8.11.8 to 8.11.10, which deal specii cally with triggered circuits.
