Hardware Reference
In-Depth Information
Figure 5.6
Trivial one-shot circuits. (a) Basic version, for synchronous input only. (b) Preceded by a
synchronizing DFF, so the input can be asynchronous. (c) With a two-stage synchronizer.
Figure 5.7
One-shot state machine. (a) Circuit ports. (b) Example of expected behavior. (c) State transition
diagram. (d) An inferior solution (exercise 5.5).
In fact, a one-shot circuit (not employing the FSM approach) was already seen in
chapter 2 (i gure 2.10), with its schematic repeated in i gure 5.6a. This option, however,
is i ne only if the triggering input ( x ) is synchronous; otherwise, the output pulse could
last less than T clk . For it to work with asynchronous inputs, another DFF is needed, as
shown in i gure 5.6b. A version with a full synchronizer (section 2.3) is shown in i gure
5.6c.
The general operating principle is illustrated in i gure 5.7. The circuit ports are
shown in i gure 5.7a, where x is the triggering input and y is the one-shot output. An
illustrative timing diagram is presented in i gure 5.7b, with x having an arbitrary dura-
tion and y lasting exactly one clock period. Pulse 1 lasts less than T clk but happened
to fall under a positive clock edge, so it was detected. This is obviously not guaranteed
to happen, as illustrated for pulse 2. Only if the duration is T clk or longer, as for pulse
3, is the triggering of y guaranteed. Note that x and y are uncorrelated (mutually
asynchronous) if x and clk are uncorrelated.
A solution using a regular (category 1) Moore machine is presented in i gure 5.7c.
Note that it stays in state B during only one clock period; because y = '1' occurs only
in that state, the desired pulse results. An inferior solution is presented in i gure 5.7d
(see exercise 5.5).
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