Hardware Reference
In-Depth Information
general purpose A and B registers, and the ALU register—ALUreg), plus a general
purpose data memory.
As usual, a control unit (FSM) is needed to control the datapath, which produces
nine signals:
AddrSource
(to control the memory address source mux),
DataSource
(to
control the register data source mux),
ALUSourceA
(to control the ALU input-A mux),
ALUSourceB
(to control the ALU input-B mux),
PCWr
(to enable writing into the
program counter register),
MemWr
(to enable writing into the memory),
MemRd
(to
enable reading the memory),
RegWr
(to enable writing into the register i le), and
ALUop
(to dei ne the ALU operation). The control unit produces these signals based on the
opcode received from the instruction register/decoder.
Each CPU instruction is broken down into a series of clock cycles, with each cycle
limited to one ALU operation plus storage or one memory/register access plus storage,
such that at the end of each cycle the data needed in the next cycle will be available
in one of the registers or in memory. For example, note in i gure 3.23 that the data
read from the memory is stored in MDR, the data from the register i le is stored in A
or B, and the ALU result is stored in ALUreg.
Two partial examples of instructions executed by the CPU of i gure 3.23 are depicted
in i gure 3.24, concerning the store word (SW) and load word (LW) instructions. As
shown in i gure 3.24a, SW is composed of two main parts: SetAddr, in which the
memory address to which data will be written is set, and WriteMem, which causes
the data to be effectively stored (at the end of that state, as explained earlier). Note
the following in the SetAddr state:
ALUSourceA
= '0', so port A of the ALU is fed by
register A;
ALUSourceB
= '1', so port B of the ALU is fed by the IR; and
ALUop
= add,
meaning that the actual opcode will cause the ALU to add its inputs, thereby pro-
ducing the intended memory address stored in ALUreg. Note the following in the
WriteMem state:
AddrSource
= '1', so the address comes from the ALU register (as
expected); and
MemWr
= '1', so writing is enabled and will occur at the next (posi-
tive) clock edge. As a i nal remark, note that the list of outputs is not the same in
both states (it should be for hardware-based implementations), which was done here
just for simplicity.
Figure 3.24
Partial state machines implementing memory access using the datapath of i gure 3.23. Recall
that in an actual design the list of outputs has to be exactly the same in all states of an FSM.
