Hardware Reference
In-Depth Information
The LW instruction, depicted in i gure 3.24b, is composed of three main parts:
SetAddr, responsible for setting the memory address from which data must be read;
ReadMem, which causes the data to be effectively read (at the end of this state); and
WriteReg, which causes the read data to be stored in one of the IR registers (again, at
the end of the state). The SetAddr state is similar to the previous case. Note the fol-
lowing in the ReadMem state: AddrSourceA = '1', so the address comes from the ALU
register (as expected); and MemRd = '1', so reading is enabled and the data will be
stored in MDR at the next (positive) clock edge. Finally, note the following in the
WriteReg state: DataSourceA = '0', so the data must come from MDR (as expected); and
RegWr = '1', so the data will be written into the register pointed to by the IR at the
next (positive) clock edge.
The reasoning used in the instructions above can be extended to all instructions
of a CPU, resulting in a generally large set of small state machines, collectively respon-
sible for implementing all of a CPU's instructions.
Points to Remember when Designing a Control Unit
We close this section with some comments that can be helpful for the proper under-
standing and correct design of FSMs for datapath control.
1) Sequential circuit and Moore machine: The control unit is normally the only sequen-
tial circuit in a datapath-based design (except for the PC, but this is just a basic counter;
registers are also clocked and so can be memories, but these act just as data storage
elements), and its design is normally based on the FSM approach. Moreover, because
control units are inherently synchronous, the Moore approach is generally preferred
(over Mealy). In the comments that follow, it is assumed that the Moore model was
adopted.
2) No direct data access: Even though the control unit is responsible for sequencing
all datapath computations, it normally does not access the actual data directly (except
for occasional trivial data monitoring).
3) Late data storage: Data storage in a datapath-based design is controlled by a write-
enable signal produced by the control unit. Because such a signal will be ready only
after the clock edge that causes the machine to enter the write-enabling state, the
actual writing will only occur at the next clock edge, that is, at the end of that state (in
other words, it will occur just prior the moment at which the machine leaves the
write-enabling state).
4) Dependency on input data: In some applications the machine must read/write data
and, based on the data value, make a decision on which state to go to next. Because
the data will be available only when the machine leaves the read/write state, the deci-
sion can obviously not be made yet. In such cases, a wait state must be included before
the decision can be made. This is illustrated in i gure 3.25. Assume that we are using
a datapath similar to that in i gure 3.22a, where the inputs must be stored in registers
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