Hardware Reference
In-Depth Information
(during one clock cycle),
inpA
and
inpB
must be added and the result stored in register
A (so we can assume
opcode
=
dv
).
The overall datapath operation is illustrated in the timing diagram of i gure 3.22c
(as usual, small propagation delays were left between the clock transitions and the
corresponding responses to portray a more realistic situation), which shows the
system clock (
clk
), the data-valid bit (
dv
), the four signals to be produced by the FSM
(
selA
,
wrA
,
wrB
,
ALUop
), and, i nally, the machine's state (
pr_state
) after every positive
clock transition.
A very important aspect to observe, which often causes confusion and leads to
incorrect designs, is how data is stored in datapaths. Because the control unit does
not access the data directly but just provides the proper path for it, the storage occurs
at the end
of any write-enabling state. For example, note in i gure 3.22c that
wrA
=
wrB
= '1' in the
load
state, which means that at the
next
clock edge (thus, at the
end
of the
load
state) the inputs will be stored in A and B (see comments at the bottom of the
i gure). The same is true in the
store
state; because
wrA
= '1' in it, at the
next
clock
edge (
end
of that state), the sum will be stored in A.
A corresponding Moore-type solution is presented in i gure 3.22d, which is a direct
translation of i gure 3.22c (compare the values in the plots against those in the state
transition diagram). Note also in i gure 3.22d that the list of outputs is
exactly the same
in all three states, as required for hardware-implemented (as opposed to software-
implemented) FSMs, otherwise latches would be inferred (unless the optional output
register is included).
The next example (i gure 3.23) shows a relatively complete CPU datapath (based
on MIPS [Patterson & Hennessy, 2011]). It contains an ALU, four multiplexers (memory
address source, register data source, ALU source A, and ALU source B), several registers
(instruction register—IR, memory data register—MDR, general purpose register i le,
Figure 3.23
A CPU datapath (based on the MIPS architecture).
