Hardware Reference
In-Depth Information
Figure 3.17
Storing the i nal result. (a-c)
dv
lasts the entire process, so its falling edge is used to activate the
output register. (d-f)
dv
lasts only one clock period, so the falling edge of
busy
is used to activate
the register.
The alternative in i gure 3.17b is obviously safe, but using the negative edge implies
that the output value has to be ready within
T
clk
/2, which might reduce the circuit's
maximum speed.
Figures 3.17d,e illustrate the more usual case in which
dv
lasts only one clock cycle,
so an auxiliary signal (called
busy
in the i gures) is needed to activate the register in
i gure 3.17f. To produce
busy
from
dv
, a pulse stretcher (studied in section 8.11.10)
can be used. However, because
busy
behaves exactly like
dv
in i gures 3.17a,b, the same
limitations apply here.
A completely different approach is presented in i gure 3.18. Note that, contrary to
the alternatives in i gure 3.17, which do not employ the actual clock to store the i nal
result,
clk
itself is used to activate the output register in i gure 3.18b, with
dv
used
