Hardware Fundamentals — Part II - Finite State Machines in Hardware - page 60

Figure 3.18
Truly synchronous alternative for storing the i nal result, which consists of producing an enable
signal, so the actual clock is responsible for activating the register.
simply to produce an enable ( ena ) signal. The result is a truly synchronous, safe imple-
mentation. Two versions of ena are shown, updated either at the positive ( ena +) or
negative ( ena -) clock edge, which can be selected according to the application. This
kind of circuit (pulse shifter) is studied in section 8.11.9.
3.12 Multimachine Designs
State machine decomposition, also called state machine factoring, refers to FSMs
that are split into two or more machines to ease the design or to take advantage
of machines that have been designed previously. In more general terms, two or more
smaller FSMs are associated in order to produce the same results as a larger, more
complex machine.
Typical associations/decompositions are depicted in i gures 3.19a-c. A series
(cascade) association is illustrated in i gure 3.19a; a parallel association is shown in
i gure 3.19b; i nally, an internal association (one machine is called as part of the other)
is depicted in i gure 3.19c.
An actual example is depicted in i gure 3.19d, which shows an association that falls
in the case of i gure 3.19c. The main FSM is a factorial ( f = n !) calculator (details can
be seen in exercise 11.9), so a multiplier is needed; because a multiplier can also be
implemented using the FSM approach (see section 11.7.5), the latter is called as part
of the former.
Another interesting example is presented in i gure 3.20a, which shows a machine
with a pair of states that need to be repeated a number of times. If T is large (say
64; therefore, 130 states), it is impractical to represent this circuit as a regular FSM.
A solution for this problem is presented in i gure 3.20b, with the original circuit
decomposed into two machines, the i rst with three states, the other with two states,
regardless of the value of T . Note that the main machine has a “superstate” (SS)
that simply enables the secondary machine to run. When ena = '0', the secondary
machine remains in the reset state, whereas ena = '1' causes it to l ip back and forth
between states B and C during 2 T clock cycles (recall that the timer's initial value