Hardware Reference
In-Depth Information
i rst clock edge occurs
after
the machine is in state B, bit 2 is captured by
y
(0) instead
of bit 1).
The same FSM is used in i gure 3.16c. However, even though the data (
dv
and
x
)
and the auxiliary register (for
y
) are still updated at the positive clock edge, the FSM
and its timer operate now at the negative clock transition. Note in the accompanying
timing diagram in i gure 3.16d that again the proper values are produced for
t
(recall
that, by default, the timer is zeroed every time the FSM changes state, and here it is
kept stopped at zero in the states where it is not needed—state A in this example),
but now all bits are captured properly, resulting, in the end,
y
(3:0) = “1101”.
A i nal solution is shown in i gure 3.16e, which consists of using a Mealy machine
instead of a Moore machine. Note in the accompanying timing diagram, in i gure
3.16f, that this machine too works well, and now the default clocking scheme (every-
body operating at the same clock edge) is employed.
Both solutions above require an auxiliary register (for
y
). This kind of FSM will be
studied in detail in chapter 11.
3.11 Storing the Final Result
This section discusses another need that sometimes arises in hardware imple-
mentations. It consists of wanting the i nal result from one run of a process to
remain stable (constant, exhibited on a display, for example) until another run
is completed, with the new result replacing the old one and also remaining
unchanged until the next value is produced, and so on. It is also common in such
cases to have a control signal (
dv
, data-valid) that indicates when the input data
is ready, so data processing should commence. The
dv
signal, which generally
lasts one clock period but can also last for the entire process, can help produce the
desired feature.
Figures 3.17a,b illustrate the case of
dv
lasting for the entire process (as usual, a
small propagation delay was included between a clock edge and its response in order
to portray a realistic situation). Note that in i gure 3.17a,
dv
is updated at the positive
clock edge, which is the same edge at which the circuit operates (see the waveform
for
output
), whereas in i gure 3.17b,
dv
is updated at the negative clock edge. As shown
in i gure 3.17c, the negative edge of
dv
is used to store the i nal result (assumed to be
output = e
; see gray shade) into an auxiliary register. This result will obviously remain
unchanged until a new result overwrites it.
The problem with the alternative in i gure 3.17a is that the output value is unlikely
to have had enough time to settle, so an incorrect value will probably be registered.
This alternative would be unsafe even if
dv
lasted an extra clock period because of the
time delay between the edges of
clk
and
dv
.
